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TMS320C44 Datasheet(PDF) 39 Page - Texas Instruments

Part # TMS320C44
Description  DIGITAL SIGNAL PROCESSOR
PDF  42 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TMS320C44 Datasheet(HTML) 39 Page - Texas Instruments

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TMS320C44
DIGITAL SIGNAL PROCESSOR
SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing for communication-token transfer sequence, output to an input port [P = tc(H)]
(see Figure 26)
NO.
MIN
MAX
UNIT
1‡
td(CRQL - CAL)T
Delay time, CREQx low to start of CACKx going low for
token-request-acknowledge
P+5
2P + 22
ns
2‡
td(CRDYL - CAL)T
Delay time, CRDYx low at end of word-transfer out to start of CACKx going low
P+6
2P + 27
ns
3
td(CAL - CD)I
Delay time, start of CACKx going low to CxDx change from outputs to inputs
0.5P – 8
0.5P + 8
ns
4
td(CAL - CRDY)T
Delay time, start of CACKx going low to CRDYx change from an input to output,
high level
0.5P – 8
0.5P + 8
ns
5‡
td(CRQH - CRQ)T
Delay time, CREQx high to CREQx change from an input to output, high level
4
22
ns
6‡
td(CRQH - CA)T
Delay time, CREQx high to CACKx change from output to an input
4
22
ns
7‡
td(CRQH - CS)T
Delay time, CREQx high to CSTRBx change from output to an input
4
22
ns
8‡
td(CRQH - CRQL)T
Delay time, CREQx high to CREQx low for the next token-request
P–4
2P + 8
ns
9
td(CAL - CDIRH)
Delay time, CACKx low to CDIRx high, change from output to input
0.5P – 8
0.5P + 10
ns
† These values are characterized but not tested.
‡ These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
CREQx
CACKx
CSTRBx
CxDx
CRDYx
= When signal is an input (clear = when signal is an output).
Valid Data
1
5
6
7
8
3
4
2
Valid Data
CDIRx
9
NOTE A: Before the token exchange, CACKx, CSTRBx, and CxD7 – CxD0 are asserted by the ’C44 sending data. CREQx and CRDYx are
input signals asserted by the ’C44 receiving data and are asynchronous with respect to the H1 clock of the sending ’C44. After token
exchange, CREQx and CRDYx become outputs, and CSTRBx, CACKx, and CxD7 – CxD0 become inputs.
Figure 26. Communication-Token Transfer Sequence, Output to an Input Port [P = tc(H)]



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