TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

34

POST OFFICE BOX 1443

NO

TMS320C44- 50

TMS320C44 - 60

UNIT

NO.

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

1

tsu(IIOF-H1L )

Setup time, IIOFx before H1 low

11†

11†

ns

2

tw(INT )

Pulse duration, to assure one interrupt seen

(see Note 11)

P

1.5P

< 2P‡

P

1.5P

< 2P‡

ns

† If this timing is not met, the interrupt is recognized in the next cycle.

‡ This value only applies to level-triggered interrupts and is specified by design but not tested.

NOTES:

9. IIOFx is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact

sequence shown occurs; otherwise, an additional delay of one clock cycle can occur.

10. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists.

11. Level-triggered interrupts require interrupt-pulse duration of at least 1P wide (P = one H1 period) to assure it will be seen. It must

be less than 2P wide to assure it will be responded to only once. Recommended pulse duration is 1.5P.

Reset or

Interrupt

Vector Read

Fetch First

Instruction of

Service

Routine

H3

H1

IIOFx

FLAGx

(IIF Register)

Address

Data

Vector

Address

First

Instruction

Address

1

2

(see Note A)

NOTE A: The ’C44 can accept an interrupt from the same source every two H1 clock cycles.