TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031B – AUGUST 1994 – REVISED DECEMBER 1995

16

POST OFFICE BOX 1443

IDLE2 clock-stop power-down mode (continued)

; ––––––––––––––––––––––––––––––––––––––––––––-–-–;

; IDLE2: Macro to generate idle2 opcode

;

; –––––––––––––––––––––––––––––––––––––––––––––-––;

IDLE2

.macro

.word

06000001h

.endm

Figure 4. Example Software Subroutine Using IDLE2

IDLE2 is exited when one of the five external interrupts (NMI and IIOF3 – IIOF0) is asserted low for at least four

input clocks (two H1 cycles). The clocks then start after a delay of two input clocks (one H1 cycle). The clocks

can start in the opposite phase; that is, H1 can be high when H3 was high before the clocks were stopped.

However, the H1 and H3 clocks remain 180 degrees out of phase with each other.

During IDLE2 operation, an external interrupt can be recognized and serviced by the CPU if it is enabled before

entering IDLE2 and asserted for at least two H1 cycles. For the processor to recognize only one interrupt, the

interrupt pin must be configured for edge-trigger mode or asserted less than three cycles in level-trigger mode.

Any external interrupt pin can wake up the device from IDLE2, but for the CPU to recognize that interrupt, it must

also be enabled. If an interrupt is recognized and executed by the CPU, the instruction following the IDLE2

instruction is not executed until after a return opcode is executed.

When the device is in emulation mode, the CPU executes an IDLE2 instruction as if it were an IDLE instruction.

The clocks continue to run for correct operation of the emulator.

boot-loader mode selection

Table 3. Boot-Loader Mode Selection Using Pins IIOF3 – IIOF0

EXTERNAL PIN

SOURCE PROGRAM LOCATION

IIOF3

IIOF2

IIOF1

IIOF0

SOURCE PROGRAM LOCATION

1

1

0

1

Load source program from address 0030 0000h

1

0

1

1

Load source program from address 4000 0000h (see Note 1)

1

0

0

1

Load source program from address 80 0000h

0

1

1

1

Load source program from address 8000 0000h (see Note 2)

0

1

0

1

Load source program from address 8040 0000h (see Note 3)

0

0

1

1

Load source program from address 8080 0000h (see Note 4)

0

0

0

1

Reserved (boot-loader program terminates)

1

1

1

1

Load source program from communication port

NOTES:

1. This selection cause the ’C44 to drive 0 in the 24 external local address pins and activates the LSTRB0 signal.

2. This selection cause the ’C44 to drive 0 in the 24 external global address pins ando activates the STRB0 signal.

3. This selection cause the ’C44 to drive 0x40 0000 in the 24 external global address pins and activates the STRB0 signal.

4. This selection cause the ’C44 to drive 0x80 0000 in the 24 external global address pins and to activate the STRB0 signal.