TMS320F243FN datasheet(63/116 Pages) TI

63 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

addressing modes (continued)

There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by adding or

subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed

addressing [used in Fast Fourier Transforms (FFTs)] with increment or decrement. All operations are performed

on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary

In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There

are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained

in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the

second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need

to be stored or used more than once during the course of program execution (for example, initialization values

or constants).

The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference

to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case,

operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand

address or immediate value.

repeat feature

The repeat function can be used with instructions (as defined in Table 21) such as multiply/accumulates (MAC

and MACD), block moves (BLDD and BLPD), I/O transfers (IN/OUT ), and table read/writes (TBLR/TBLW ).

These instructions, although normally multicycle, are pipelined when the repeat feature is used, and they

effectively become single-cycle instructions. For example, the table-read instruction can take three or more

cycles to execute, but when the instruction is repeated, a table location can be read every cycle.

The repeat counter (RPTC) is loaded with the addressed data memory location if direct or indirect addressing

is used, and with an 8-bit immediate value if short-immediate addressing is used. The internal RPTC register

is loaded by the RPT instruction. This results in a maximum of N + 1 executions of a given instruction. RPTC

is cleared by reset. Once a repeat instruction (RPT ) is decoded, all interrupts, including NMI (but excluding

reset), are masked until the completion of the repeat loop.

instruction set summary

This section summarizes the operation codes (opcodes) of the instruction set for the ’x24x digital signal

processors. This instruction set is a superset of the ’C1x and ’C2x instruction sets. The instructions are arranged

according to function and are alphabetized by mnemonic within each category. The symbols in Table 20 are

used in the instruction set summary table (Table 21). T he TI ’C2xx assembler accepts ’C2x instructions.

The number of words that an instruction occupies in program memory is specified in column 3 of Table 22.

Several instructions specify two values separated by a slash mark ( / ) for the number of words. In these cases,

different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies

one word when the operand is a short-immediate value or two words if the operand is a long-immediate value.

The number of cycles that an instruction requires to execute is also in column 3 of Table 22. All instructions are

assumed to be executed from internal program memory (RAM) and internal data dual-access memory. The

cycle timings are for single-instruction execution, not for repeat mode.

TMS320F243FN Datasheet(PDF) 63 Page - Texas Instruments

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