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TMS320F243FN Datasheet(PDF) 28 Page - Texas Instruments |
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TMS320F243FN Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 116 page  TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 hardware-generated interrupts (continued) CPU IACK Bus Addr Bus Data PIVR & logic PIRQR# PIACK# IRQ GEN Level 6 IRQ GEN Level 5 IRQ GEN Level 4 IRQ GEN Level 3 IRQ GEN Level 2 IRQ GEN Level 1 XINT2 XINT1 ADCINT CANERINT CANMBINT TXINT RXINT SPIINT CAPINT3 CAPINT2 CAPINT1 TOFINT2 TUFINT2 TCINT2 TPINT2 TOFINT1 TUFINT1 TCINT1 TPINT1 CMP3INT CMP2INT CMP1INT CANERINT CANMBINT TXINT RXINT SPIINT XINT2 XINT1 ADCINT PDPINT INT1 INT2 INT3 INT4 INT6 INT5 IMR IFR IRQ Pulse Gen Unit Figure 6. Peripheral Interrupt Expansion Block Diagram interrupt hierarchy The number of interrupt requests available is expanded by having two levels of hierarchy in the interrupt request system. There are two levels of hierarchy in both the interrupt request/acknowledge hardware and in the interrupt service routine software. |
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