| Electronic Components Datasheet Search |
|
TMS320F243FN Datasheet(PDF) 27 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMS320F243FN Datasheet(HTML) 27 Page - Texas Instruments |
|
27 / 116 page ![]() TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999 27 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 reset The reset operation ensures an orderly startup sequence for the device. There are two possible causes of a reset, as shown in Figure 5. Signal Reset System Reset Watchdog Timer Reset External Reset (RS) Pin Active Figure 5. Reset Signals The two possible reset signals are generated as follows: D Watchdog timer reset. A watchdog-timer-generated reset occurs if the watchdog timer overflows or an improper value is written to either the watchdog key register or the watchdog control register. (Note that when the device is powered on, the watchdog timer is automatically active.) The watchdog timer reset is reflected on the external RS pin also. D Reset pin active. To generate an external reset pulse on the RS pin, a low-level pulse duration of at least one CPUCLK cycle is necessary to ensure that the device recognizes the reset signal. Once watchdog reset is activated, the external RS pin is driven (active) low for a minimum of eight CPUCLK cycles. This allows the TMS320x24x device to reset external system components. The occurrence of a reset condition causes the TMS320x24x to terminate program execution and affects various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are affected by a reset are initialized to their reset state. hardware-generated interrupts The ’24x CPU supports one nonmaskable interrupt (NMI) and six maskable prioritized interrupt requests. The ’24x devices have many peripherals, and each peripheral is capable of generating one or more interrupts in response to many events. The ’24x CPU does not have sufficient interrupt requests to handle all these peripheral interrupt requests; therefore, a centralized interrupt controller is provided to arbitrate the interrupt requests from all the different sources. Throughout this section, refer to Figure 6 . |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |