TMS320F243FN datasheet(22/116 Pages) TI

22 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

software-controlled wait-state generator

Due to the fast cycle time of the ’F243 devices, it is often necessary to operate with wait states to interface with

external logic or memory. For many systems, one wait state is adequate.

The software wait-state generator can be programmed to generate between 0 and 7 wait states for a given

space. Software wait states are configured through the wait-state generator register (WSGR). The WSGR

includes three 3-bit fields to configure wait states for the following external memory spaces: data space (DSWS),

program space (PSWS), and I/O space (ISWS). The wait-state generator enables wait states for a given

memory space based on the value of the corresponding three bits, regardless of the condition of the READY

signal. The READY signal can be used to generate additional wait states. All bits of the WSGR are set to 1 at

reset so that the device can operate from slow memory at reset. The WSGR register (shown in Table 3, Table 4

and Table 5) resides at I / O location FFFFh. This register should not be accessed in the ’F241.

Table 3. Wait-State Generator Control Register ( WSGR)

Reserved

BVIS

ISWS

DSWS

PSWS

R/W–11

R/W–111

LEGEND:

0 = Always read as zeros, R = Read Access, W= Write Access, – n = Value after reset

Table 4. Wait-State(s) Programming

PSWS, DSWS, ISWS BITS

WAIT STATES FOR PROGRAM, DATA, OR I / O

000

001

010

011

100

101

110

111

Table 5. Wait-State Generator Control Register ( WSGR)

BITS

NAME

DESCRIPTION

2–0

PSWS

External program space wait states. PSWS determines that between 0 to 7 wait states are applied to all reads

and writes to off-chip program space address. The memory cycle can be further extended by using the READY

signal. The READY signal does not override the wait states generated by PSWS. These bits are set to 1 (active)

by reset (RS).

5–3

DSWS

External data space wait states. DSWS determines that between 0 to 7 wait states are applied to all reads and

writes to off-chip data space. The memory cycle can be further extended by using the READY signal. The READY

signal does not override the wait states generated by DSWS. These bits are set to 1 (active) by reset (RS).

8–6

ISWS

External input / output space wait state. ISWS determines that between 0 to 7 wait states are applied to all reads

and writes to off-chip I / O space. The memory cycle can be further extended by using the READY signal. The

READY signal does not override the wait states generated by ISWS. These bits are set to 1 (active) by reset (RS).

10 – 9

BVIS

Bus visibility modes. Bits 10 and 9 allow selection of various bus visibility modes while running from internal

program and/or data memory. These modes provide a method of tracing internal bus activity. These bits are set

to 11b by reset (RS), causing internal program address and program data to be output on the external address

and data pins. See Table 6.

15 – 11

–

Reserved

TMS320F243FN Datasheet(PDF) 22 Page - Texas Instruments

TMS320F243FN Datasheet(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL