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TMS320F243FN Datasheet(PDF) 98 Page - Texas Instruments |
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TMS320F243FN Datasheet(HTML) 98 Page - Texas Instruments |
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98 / 116 page  TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999 98 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 external memory interface ready-on-read timings switching characteristics over recommended operating conditions for an external memory interface ready-on-read (see Figure 40) PARAMETER MIN MAX UNIT td(COL–A)RD Delay time, CLKOUT low to address valid 5 ns timing requirements for an external memory interface ready-on-read (see Figure 40) MIN MAX UNIT th(RDY)COH Hold time, READY after CLKOUT high –5 ns tsu(D)RD Setup time, read data before RD strobe inactive high 12 ns tv(RDY)ARD Valid time, READY after address valid on read 4 ns tsu(RDY)COH Setup time, READY before CLKOUT high 17 ns th(RDY)COH CLKOUT PS, DS, IS, BR RD D[0:15] STRB A[0:15] td(COL–A)RD tv(RDY)ARD tsu(RDY)COH READY Wait Cycle tsu(D)RD Figure 40. Ready-on-Read Timings |
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