TMS320F243FN datasheet(64/116 Pages) TI

64 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

instruction set summary (continued)

Table 20. TMS320x24x Opcode Symbols

SYMBOL

DESCRIPTION

Address

ACC

Accumulator

ACCB

Accumulator buffer

ARx

Auxiliary register value (0 – 7)

BITx

4-bit field that specifies which bit to test for the BIT instruction

BMAR

Block-move address register

DBMR

Dynamic bit-manipulation register

Addressing-mode bit

II...II

Immediate operand value

INTM

Interrupt-mode flag bit

INTR#

Interrupt vector number

Constant

PREG

Product register

PROG

Program memory

RPTC

Repeat counter

SHF, SHFT

3/4-bit shift value

Test-control bit

T P

Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO.

T P

Meaning

0 0

BIO low

0 1

TC = 1

1 0

TC = 0

1 1

None of the above conditions

TREGn

Temporary register n (n = 0, 1, or 2)

Z L V C

4-bit field representing the following conditions:

ACC = 0

ACC < 0

Overflow

Carry

A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the

corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 4 – 7) indicates the state of

the conditions designated by the mask bits as being tested. For example, to test for ACC

≥ 0, the Z and L fields are set while

the V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate

testing of the condition ACC = 0, and the L field is reset to indicate testing of the condition ACC

≥ 0. The conditions possible

with these 8 bits are shown in the BCND and CC instructions. To determine if the conditions are met, the 4-LSB bit mask

is ANDed with the conditions. If any bits are set, the conditions are met.

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