TMS370 datasheet(8/43 Pages) TI

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TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

256-Byte RAM (0000h–00FFh)

Peripheral File

Reserved†

7FC0h – 7FDFh

PACT Interrupt 1-18

7FEEh – 7FF7h

Reserved†

7FECh –7FEDh

Interrupt 1

Reset

1020h – 102Fh

Digital Port Control

Vectors

ADC1

7FFCh – 7FFDh

7FFEh – 7FFFh

0000h

0100h

0080h

0FFFh

1000h

10BFh

10C0h

1EFFh

1F00h

1FFFh

2000h

5FFFh

6000h

FFFFh

00FFh

Interrupts and Reset Vectors;

Trap and PACT Vectors

7F9Bh

7F9Ch

7FFFh

8000h

7FF8h – 7FF9h

7FFAh – 7FFBh

Peripheral File Control Registers

1010h – 101Fh

1050h – 105Fh

System Control

1030h – 103Fh

1040h – 104Fh

ADC1 Peripheral Control

Trap 15 – 0

Reserved†

256-Byte Data EEPROM

Reserved†

8K-Byte ROM/EPROM

Reserved†

7F9Ch – 7FBFh

7FE0h – 7FEBh

1000h – 100Fh

1060h – 106Fh

1070h – 107Fh

Reserved†

PACT Peripheral Control

Reserved†

Interrupt 2

Interrupt 3

Dual–Port RAM (0080h–00FFh)

† Reserved means that the address space is reserved for future expansion.

Figure 3. TMS370Cx32 Memory Map

RAM / register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read / write memory, program

memory, or the stack instructions. The TMS370Cx32 devices contain 256 bytes of internal RAM,

memory-mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is

shown in Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly

use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the

stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

dual-port RAM

The upper 128 bytes of the register files (0080h – 00FFh) can be used by the PACT module to contain

commands and definitions as well as timer values. Any RAM not used by PACT can be used as additional CPU

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