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TMS370 Datasheet(PDF) 31 Page - Texas Instruments |
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TMS370 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 43 page  TMS370Cx32 8-BIT MICROCONTROLLER SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997 31 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table 17 is a collection of all the peripheral file frames used in the ’Cx32 (provided for a quick reference). Table 17. Peripheral File Frame Compilation System Configuration Registers PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P010 COLD START OSC POWER PF AUTO WAIT OSC FLT FLAG MC PIN WPO MC PIN DATA — µP/ µC MODE SCCR0 P011 — — — AUTO WAIT DISABLE — MEMORY DISABLE — — SCCR1 P012 HALT / STANDBY PWRDWN / IDLE — BUS STEST CPU STEST — INT1 NMI PRIVILEGE DISABLE SCCR2 P013 to P016 Reserved P017 INT1 FLAG INT1 PIN DATA — — — INT1 POLARITY INT1 PRIORITY INT1 ENABLE INT1 P018 INT2 FLAG INT2 PIN DATA — INT2 DATA DIR INT2 DATA OUT INT2 POLARITY INT2 PRIORITY INT2 ENABLE INT2 P019 INT3 FLAG INT3 PIN DATA — INT3 DATA DIR INT3 DATA OUT INT3 POLARITY INT3 PRIORITY INT3 ENABLE INT3 P01A BUSY — — — — AP W1W0 EXE DEECTL P01B Reserved P01C BUSY VPPS — — — — W0 EXE EPCTLL P01D P01E P01F Reserved Digital Port Control Registers P020 Reserved APORT1 P021 Port A Control Register 2 (must be 0) APORT2 P022 Port A Data ADATA P023 Port A Direction ADIR P024 to P02B Reserved P02C Port D Control Register 1 (must be 0) — Port D Control Register 1 (must be 0) — — — DPORT1 P02D Port D Control Register 2 (must be 0)† — Port D Control Register 2 (must be 0)† — — — DPORT2 P02E Port D Data — Port D Data — — — DDATA P02F Port D Direction — Port D Direction — — — DDIR PACT Module Register Memory Map P040 DEFTIM OVRFL INT ENA DEFTIM OVRFL INT FLAG CMD/DEF AREA ENA FAST MODE SELECT PACT PRESCALE SELECT3 PACT PRESCALE SELECT2 PACT PRESCALE SELECT1 PACT PRESCALE SELECT0 PACTSCR P041 CMD/DEF AREA INT ENA — CMD/DEF AREA START BIT 5 CMD/DEF AREA START BIT 4 CMD/DEF AREA START BIT 3 CMD/DEF AREA START BIT 2 — — CDSTART † To configure D3 as SYSCLK, set port D register 2 = 08h. |
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