TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997

2

POST OFFICE BOX 1443

Pin Descriptions

44 PINS

I/O†

DESCRIPTION

NAME

NO.

I/O†

DESCRIPTION

A0

A1

A2

A3

A4

A5

A6

A7

20

19

18

17

16

15

13

12

I/O

Port A is a general-purpose bidirectional I / O port.

D3

D4/CP3

D6/CP4

D7/CP5

23

22

24

21

I/O

Port D is a general-purpose bidirectional port.

Also configurable as SYSCLK (see Note 1)

PACT input capture 3 (see Note 2)

PACT input capture 4 (see Note 2)

PACT input capture 5 (see Note 2)

CP1

CP2

CP6

40

36

34

I

PACT Input capture pin 1

PACT Input capture pin 2

PACT Input capture pin 3

AN0/E0

AN1/E1

AN2/E2

AN3/E3

AN4/E4

AN5/E5

AN6/E6

AN7/E7

25

26

27

28

30

31

32

33

I

ADC1 analog input pins (AN0 – AN7) / port E digital input pins (E0 – E7)

Port E can be programmed individually as a general-purpose digital input pin if it is not used as ADC1 analog

input or positive reference input.

INT1

INT2

INT3

7

8

9

I

I/O

I/O

External interrupt (non-maskable or maskable) / general-purpose input pin

External maskable interrupt input/general purpose bidirectional pin

External maskable interrupt input/general purpose bidirectional pin

OP1

OP2

OP3

OP4

OP5

OP6

OP7

OP8

42

43

44

1

2

3

4

5

O

PACT output pin 1

PACT output pin 2

PACT output pin 3

PACT output pin 4

PACT output pin 5

PACT output pin 6

PACT output pin 7

PACT output pin 8

SCIRXD

SCITXD

35

41

I

O

PACT mini SCI data receive input pin

PACT mini SCI data transmit output pin

RESET

6

I/O

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output,

RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit.

MC

39

I

Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM VPP

XTAL2 / CLKIN

XTAL1

38

37

I

O

Internal oscillator crystal input / External clock source input

Internal oscillator output for crystal

VCC1

VSS1

VCC3

VSS3

10

14

11

29

Positive supply voltage for digital logic and digital I/O pins

Ground reference for digital logic and digital I/O pins

ADC1 positive supply voltage and optional positive reference input

ADC1 ground supply and low reference input pin

† I = input, O = output

NOTES:

1. D3 can be configured as SYSCLK by appropriately programming the DPORT1 and DPORT2 registers.

2. These digital I/O buffers are connected internally to some of the PACT module’s input capture pins. This allows the microcontroller

to read the level on the input capture pin, or if the port D pin is configured as an output, to generate a capture. Be careful to leave

the port D pin configured as an input if the corresponding input capture pin is being driven by external circuitry.