TMS370 datasheet(14/43 Pages) TI

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TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts (continued)

Table 7. Hardware System Interrupts

INTERRUPT

SOURCE

INTERRUPT

FLAG

OSC FLT FLG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

MODULE

PRIORITY†

PRIORITY

GROUP

RESET

External RESET

Watchdog Overflow

Oscillator Fault

COLD START

(No Flag)

OSC FLT FLAG

RESET‡

7FFEh, 7FFFh

INT1

External Interrupt 1

INT1 FLAG

INT1‡

7FFCh, 7FFDh

INT2

External Interrupt 2

INT2 FLAG

INT2‡

7FFAh, 7FFBh

INT3

External Interrupt 3

INT3 FLAG

INT3‡

7FF8h, 7FF9h

PACT Circular Buffer

Buffer Half/Full

Interrupt Flag

BUFINT

7FB0h, 7FB1h

PACT CP6 Event

CP6 INT FLAG

CP6INT

7FB2h, 7FB3h

PACT CP5 Event

CP5 INT FLAG

CP5INT

7FB4h, 7FB5h

PACT (Group 1)

PACT CP4 Event

CP4 INT FLAG

CP4INT

7FB6h, 7FB7h

PACT (Group 1)

PACT CP3 Event

CP3 INT FLAG

CP3INT

7FB8h, 7FB9h

PACT CP2 Event

CP2 INT FLAG

CP2INT

7FBAh, 7FBBh

PACT CP1 Event

CP1 INT FLAG

CP1INT

7FBCh, 7FBDh

Default Timer

Overflow

DEFTIM OVRFL INT

FLAG

POVRL

INT

7FBEh, 7FBFh

PACT (Group 2)

PACT SCI Rx Int

PACT RX RDY

PRXINT

7F9Eh, 7F9Fh

PACT (Group 2)

PACT SCI Tx Int

PACT TX RDY

PTXINT

7F9Ch, 7F9Dh

PACT Cmd/Def Entry 0

CMD/DEF INT 0 FLAG

CDINT 0

7FA0h, 7FA1h

PACT Cmd/Def Entry 1

CMD/DEF INT 1 FLAG

CDINT 1

7FA2h, 7FA3h

PACT Cmd/Def Entry 2

CMD/DEF INT 2 FLAG

CDINT 2

7FA4h, 7FA5h

PACT (Group 3)

PACT Cmd/Def Entry 3

CMD/DEF INT 3 FLAG

CDINT 3

7FA6h, 7FA7h

PACT (Group 3)

PACT Cmd/Def Entry 4

CMD/DEF INT 4 FLAG

CDINT 4

7FA8h, 7FA9h

PACT Cmd/Def Entry 5

CMD/DEF INT 5 FLAG

CDINT 5

7FAAh, 7FABh

PACT Cmd/Def Entry 6

CMD/DEF INT 6 FLAG

CDINT 6

7FACh, 7FADh

PACT Cmd/Def Entry 7

CMD/DEF INT 7 FLAG

CDINT 7

7FAEh, 7FAFh

ADC1

ADC1 Conversion Complete

AD INT FLAG

ADINT

7FECh, 7FEDh

† Relative priority within an interrupt level

‡ Release microcontroller from STANDBY and HALT low-power modes

privileged operation and EEPROM write protection override

The TMS370Cx32 family is designed with significant flexibility to enable the designer to software-configure the

system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of

operation ensures the integrity of the system configuration, once it is defined for an application. Following a

hardware reset, the TMS370Cx32 operates in the privileged mode, where all peripheral file registers have

unrestricted read / write access, and the application program configures the system during the initialization

sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is

set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within

the PF. Table 8 displays the system-configuration bits which are write-protected during the nonprivileged mode

and must be configured by software prior to exiting the privileged mode.

TMS370 Datasheet(PDF) 14 Page - Texas Instruments

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