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TMS370 Datasheet(PDF) 49 Page - Texas Instruments |
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TMS370 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 60 page  TMS370Cx2x 8-BIT MICROCONTROLLER SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997 49 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SPI master mode external timing characteristics and requirements (see Note 12 and Figure 24) NO. MIN MAX UNIT 38 tc(SPC)M Cycle time, SPICLK 2tc 256tc ns 39 tw(SPCL)M Pulse duration, SPICLK low tc – 45 0.5tc(SPC)+45 ns 40 tw(SPCH)M Pulse duration, SPICLK high tc – 55 0.5tc(SPC)+45 ns 41 td(SPCL-SIMOV)M Delay time, SPISIMO valid after SPICLK low (polarity = 1) – 65 50 ns 42 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (polarity =1) tw(SPCH) – 50 ns 43 tsu(SOMI-SPCH)M Setup time, SPISOMI to SPICLK high (polarity = 1) 0.25 tc + 150 ns 44 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (polarity = 1) 0 ns NOTE 12 : tc = system-clock cycle time = 1 /SYSCLK Data Valid Data Valid SPISOMI SPISIMO SPICLK 44 43 42 41 38 40 39 NOTE A: The diagram is for polarity = 1. SPICLK is inverted when polarity = 0. Figure 24. SPI Master External Timing |
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