TMS370 datasheet(29/60 Pages) TI

29 / 60 page

TMS370Cx2x

8-BIT MICROCONTROLLER

SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial peripheral interface (continued)

The SPI block diagram is listed in Figure 11.

SPIBUF Buffer

SPIDAT

Data Register

SPIBUF.7-0

State Control

SPI CHAR

SPI BIT RATE

CLOCK POLARITY

SPI INT FLAG

SPICTL.6

SPIINT ENA

SPICTL.0

RECEIVER

OVERRUN

SPIDAT.7-0

SPICTL.1

TALK

SPICCR.2-0

SPICCR.5-3

System

Clock

SPICCR.6

SPICLK

MASTER/SLAVE†

SPICTL.7

Level 2 INT

SPIPRI.6

SPIPC2.7-4

SPISIMO

SPICTL.2

SPIPC1.3-0

SPISOMI

SPIPC2.3-0

Level 1 INT

† The diagram shows slave mode.

Figure 11. SPI Block Diagram

serial communications interface 1 (SCI1)

The TMS370x2x devices include a serial communications interface 1 (SCI1) module. The SCI1 module

supports digital communications between the TMS370 devices and other asynchronous peripherals, and uses

the standard non-return-to-zero (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and

each has separate enable and interrupt bits. Both can operate independently or simultaneously in the full-duplex

mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun, and framing

errors. The bit rate (baud) is programmable to over 65,000 speeds through a 16-bit baud-select register.

TMS370 Datasheet(PDF) 29 Page - Texas Instruments

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