TMS370 datasheet(7/60 Pages) TI

7 / 60 page

TMS370Cx2x

8-BIT MICROCONTROLLER

SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

central processing unit (CPU) (continued)

Reserved†

Peripheral File

Not Available‡

0FFFh

1000h

1F00h

1FFFh

2000h

5FFFh

6000h

Interrupts and Reset Vectors;

Trap Vectors

10FFh

1100h

1EFFh

Reserved†

7FFFh

RAM (Includes up to 256-Byte Registers File)

Program Counter

Legend:

Z=Zero

IE1=Level 1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level 2 interrupts Enable

IE1

IE2

Status Register (ST)

Stack Pointer (SP)

R0(A)

R1(B)

R127

0000h

0001h

0002h

007Fh

R255

0003h

00FFh

256-Byte Data EEPROM

6FFFh

7000h

8K-Byte ROM/EPROM (6000h – 7FFFh)

4K-Byte ROM (7000h – 7FFFh)

7FC0h

7FBFh

00FFh

0100h

256-Byte RAM (0000h–00FFh)

0000h

† Reserved means the address space is reserved for future expansion.

‡ Not available means the address space is not accessible.

Figure 1. Programmer’s Model

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read / write memory. Typically the stack

is used to store the return address on subroutine calls as well as the status register contents during interrupt

sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed

onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the

on-chip RAM.

status register (ST)

The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits.

D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional-jump instructions) use the status bits to determine program flow.

D The two interrupt-enable bits control the two interrupt levels.

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