TMS370 datasheet(31/60 Pages) TI

31 / 60 page

TMS370Cx2x

8-BIT MICROCONTROLLER

SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) (continued)

The SCI1 module control registers are listed in Table 16.

Table 16. Peripheral File Frame 5: SCI1 Module Control Registers†

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P050

STOP

BITS

EVEN/ODD

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS

IDLE WUP

SCI

CHAR2

SCI

CHAR1

SCI

CHAR0

SCICCR

P051

—

SCI SW

RESET

CLOCK

TXWAKE

SLEEP

TXENA

RXENA

SCICTL

P052

Bit 15

Baud Rate Select Register MSB

Bit 8

BAUD

MSB

P053

Bit 7

Baud Rate Select Register LSB

Bit 0

BAUD

LSB

P054

TXRDY

EMPTY

—

SCI TX

INT ENA

TXCTL

P055

ERROR

RXRDY

BRKDT

RXWAKE

SCI RX

INT ENA

RXCTL

P056

Reserved

P057

Receive Data Buffer Register

RXBUF

P058

Reserved

P059

Transmit Data Buffer Register

TXBUF

P05A

P05B

Reserved

P05C

P05D

—

SCICLK

DATA IN

SCICLK

DATA OUT

SCICLK

FUNCTION

SCICLK

DATA DIR

SCIPC1

P05E

SCI TXD

DATA IN

SCI TXD

DATA OUT

SCI TXD

FUNCTION

SCI TXD

DATA DIR

SCI RXD

DATA IN

SCI RXD

DATA OUT

SCI RXD

FUNCTION

SCI RXD

DATA DIR

SCIPC2

P05F

SCI

STEST

SCI TX

PRIORITY

SCI RX

PRIORITY

SCI

ESPEN

—

SCIPRI

† Privileged bits are shown in bold typeface.

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