TMS370 datasheet(13/59 Pages) TI

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx7x CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

generated internally, while one (RESET) is controlled externally. These actions are as follows:

D External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle (it is possible, however, that a signal of less than one SYSCLK

could cause a reset). See the

TMS370 Family User’s Guide (literature number SPNU127) or the TMS370

Family Data Manual (SPNS014B) for more information.

D Watchdog (WD) timer. A watchdog-generated reset occurs when an improper value is written to the WD

key register or when the re-initialization does not occur before the watchdog timer timeout. See the

TMS370

Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (SPNS014B) for

more information.

D Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See

the

TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual

(SPNS014B) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x7x device to reset external system components. Additionally, if a cold-start condition

(e.g., VCC is off for several hundred milliseconds) exists, an oscillator failure occurs, or the RESET pin is held

low, then the reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag

(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 7 lists the reset sources.

Table 7. Reset Sources

ADDRESS

BIT NO.

CONTROL BIT NAME

SOURCE OF RESET

SCCR0

1010h

P010

COLD START

Cold (power-up)

SCCR0

1010h

P010

OSC FLT FLAG

Oscillator out of range

T1CTL2

104Ah

P04A

WD OVRFL INT FLAG

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

The CPU registers initialize: ST = 00h, SP = 01h (reset state).

Registers A and B initialize to 00h (no other RAM is changed).

The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

Program execution begins with an opcode fetch from the address pointed to by the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control

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