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TMS370 Datasheet(PDF) 14 Page - Texas Instruments

Part # TMS370
Description  8-BIT MICROCONTROLLER
PDF  59 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS370 Datasheet(HTML) 14 Page - Texas Instruments

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TMS370Cx7x
8-BIT MICROCONTROLLER
SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
interrupts
The TMS370 family software programmable interrupt structure permits flexible on-chip and external-interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of
the status register.
Each system interrupt is configured independently to either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is configured selectively on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.
The TMS370Cx7x has six hardware-system interrupts (plus RESET) as shown in Table 8. Each system
interrupt has a dedicated vector located in program memory through which control is passed to the interrupt
service routines. All of the interrupt sources are maskable individually by local interrupt-enable control bits in
the associated peripheral file (PF). Each interrupt source FLAG bit is readable individually for software polling
or for determining which interrupt source generated the associated system interrupt. The interrupt-control block
diagram is illustrated in Figure 4.



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