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TMS370 Datasheet(PDF) 27 Page - Texas Instruments |
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TMS370 Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 59 page  TMS370Cx7x 8-BIT MICROCONTROLLER SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 27 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timer 1 (T1) module (continued) D Hard watchdog configuration for mask-ROM device (see Figure 9) – Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct value is written. – Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter overflows – Automatic activation of the WD timer upon power-up reset – INT1 is enabled as nonmaskable interrupt during low-power modes – A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system reset 16-Bit Watchdog Counter Reset Prescaler Clock Watchdog Reset Key WD OVRFL TAP SEL System Reset T1CTL1.7 WDRST.7-0 WDCNTR.15-0 T1CTL2.5 WD OVRFL INT FLAG Figure 9. Hard Watchdog |
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