TMS370 datasheet(32/59 Pages) TI

32 / 59 page

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timer 2A (T2A) module (continued)

The timer 2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram

identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is

106Bh, bit 0, in the T2ACTL2 register.

Capt/Comp

T2APC2.3–0

Compare =

Clock

Source

16-Bit

Counter

MSB

LSB

T2ACNTR.15–0

Reset

T2AC1

RST ENA

T2ACTL1.0

T2ACTL3.4

T2ACTL2.6

T2ACTL2.1

T2ACTL2.7

T2ACTL2.2

T2ACTL2.5

T2ACTL2.0

16-Bit

MSB

LSB

T2ACC.15–0

T2AC.15–0

16-Bit

Compare

MSB

LSB

T2A PRIORITY

Level 1 Int

Level 2 Int

T2ACTL1.3

T2ACTL1.4

16-Bit

Capture

MSB

LSB

T2AIC.15–0

Edge 2

Select

T2AIC2/PWM

T2APC2.7–4

T2ACTL3.1

Edge1

Select

T2AIC1/CR

T2ACTL3.3

T2ACTL3.2

T2ACTL3.0

T2AEDGE1 POLARITY

T2AEDGE1 DET ENA

T2AEDGE2 DET ENA

T2AEDGE2 POLARITY

T2AC1 INT FLAG

T2AC1 INT ENA

T2A OVRFL INT FLAG

T2A OVRFL INT ENA

T2AEDGE1 INT FLAG

T2AEDGE1 INT ENA

T2AEDGE2 INT ENA

T2AEDGE2 INT FLAG

T2APRI.6

T2A SW

RESET

Figure 13. Dual-Capture Mode

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