TMS370 datasheet(18/59 Pages) TI

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

low-power and IDLE modes (continued)

Table 10. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

MODE SELECTED

STANDBY

HALT

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6–7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog is selected. This means

that the NMI always is generated, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status

registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the

STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘370Cx7x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4

(standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing

process of a TMS370 microcontroller. The ‘370Cx7x ROM-masked devices offer both options to meet system

engineering requirements. Only one of the two clock options is allowed on the ROM device while the EPROM

devices have the divide-by-4 option.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock

(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external

resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock

module then divides the resulting signal by four to provide the four-phased internal system clock signals. The

resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows:

Divide-by-4 option : SYSCLK

external resonator frequency

+ CLKIN

Divide-by-1 option : SYSCLK

external resonator frequency

+ CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of

low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators.

The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a

steeper decay of emissions produced by the oscillator.

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