TMC22091 datasheet(20/60 Pages) CADEKA

20 / 60 page

TMC22091/TMC22191

PRODUCT SPECIFICATION

Control Register Deﬁnitions (continued)

Standards Control Register (0F)

EFEN

SIX25

PALID

SETUP

YGAIN

CGAIN

Reg

Bit

Name

Function

EFEN

Same as Register 0E bit 7, but read-only.

SIX25

Select 625 lines per frame. When HIGH, the encoder assumes 625 line per

frame. When LOW, 525 lines per frame are assumed.

PALID

PAL select. When HIGH, Phase alternate line (PAL) operation is selected.

When LOW, operation conforms to NTSC standards.

SETUP

Setup enable. When HIGH, a 7.5 IRE Pedestal is added to the output video.

when LOW, no pedestal is added.

3-2

YGAIN

Luminance gain settings are adjusted to conform to the following NTSC and

PAL standards:

0 0 NTSC without SETUP

0 1 NTSC-A and PAL-M

1 0 PAL-I and PAL-N

1 1 Reserved

1-0

CGAIN

Chrominance gain settings are adjusted to conform to the following NTSC and

PAL standards:

0 0 NTSC without SETUP

0 1 NTSC-A and PAL-M

1 0 PAL-I and PAL-N

1 1 Reserved

Timing Registers (10-17)

Reg

Bit

Name

Function

7-0

Horizontal sync tip length. This 8-bit register holds a value extending from 0 to

255 PCK cycles.

7-0

Breezeway length. This 8-bit register holds a value extending from 0 to 255

PCK cycles.

7-0

Burst length. This 8-bit register holds a value extending from 0 to 255 PCK

cycles.

7-0

CBP

Color back porch length. This 8-bit register holds a value extending from 0 to

255 PCK cycles.

7-0

XBP

Extended color back porch 8 LSBs. This 8-bit register holds the LSBs of a

10-bit value extending from 0 to 1023 PCK cycles. The two MSBs are located in

control register 18.

7-0

Active video 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value

extending from 0 to 1023 PCK cycles. The two MSBs are located in control

7-0

Active video start 8 LSBs. This 8-bit register holds the LSBs of a 10-bit value

which is the initial half active video length extending from 0 to 1023 PCK cycles.

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