TMC22091 datasheet(36/60 Pages) CADEKA

36 / 60 page

TMC22091/TMC22191

PRODUCT SPECIFICATION

In read mode, the address is accompanied by a HIGH on the

R/W pin during a falling edge of CS. The data output pins go

to a low-impedance state tDOZ ns after CS falls. Valid data is

present on D7-0 tDOM after the falling edge of CS. Because

this port operates asynchronously with the pixel timing,

there is an uncertainty in this data valid output delay of one

PXCK period. This uncertainty does not apply to tDOZ.

The RESET pin restores the TMC22x91 to ﬁeld 1 line 1 and

places the encoder in a power-down state (if HRESET is

LOW). Bit 4 of the Global Control Register (SRESET) is set

LOW. All other control words and CLUT contents are left

unchanged. Returning RESET HIGH synchronizes the inter-

nal clock with PXCK and restores the device outputs to

active states.

Reading Pixel Data from the D7-0 Port

The microprocessor port of the TMC22x91 may be used to

monitor digital video outputs. The eight MSBs of the up-

sampled and interpolated pixel data that go to the

COMPOSITE D/A converter can also be accessed via the

D7-0 port. When the Test Control Register is loaded with 28h

and the Control Register pointer is loaded with 40h, the D7-0

port will output the 8-bit composite pixels synchronous with

PXCK. To halt the pixel ﬂow from D7-0, simply bring CS

HIGH.

Luminance pixel data may also be read from D7-0. In this

case, the eight MSBs of luminance at the input of the Sync

and Blank Insert block are monitored. When the Control

8-bit luminance pixels synchronous with respect to PXCK.

To halt the pixel ﬂow from D7-0, bring CS HIGH.

Operational Timing

The TMC22x91 operates in three distinct modes:

Master mode. The encoder independently produces all

internal timing and provides digital sync to the host

controller.

Slave mode. The encoder accepts horizontal and vertical

sync from the controller and synchronizes the video out-

put accordingly.

Genlock mode. The encoder accepts horizontal and ver-

tical sync from the companion TMC22071 Genlocking

Video Digitizer, synchronizes itself to the incoming

video, and provides appropriate H Sync and V Sync to

the host. It synchronizes Pixel Data input in two ways:

Internal PDC. The encoder internally generates the

Pixel Data Control (PDC) signal which calls for

data input from the external pixel source.

External PDC. The encoder receives a PDC signal

from the host and accepts Pixel Data based on that

input.

Figure 12. Reset Timing – PCK Synchronization

PXCK

RESET

tSR

tHR

24330A

tSR

Reset Timing

The TMC22x91 operates from a master clock (PXCK) at

twice the pixel rate. In Master mode, the PCK to PXCK tim-

ing relationship is set on the rising edge of RESET. In Figure

12, PCK is denoted by odd PXCK counts.

When RESET is taken LOW with sufﬁcient setup time (tSR)

before a rising edge of PXCK, the internal state machines are

reset and the device is put into a mode as dictated by the Glo-

bal Control Register bits 0 and 4. In Master mode, when the

RESET pin is taken HIGH, the internal clock timing is estab-

lished. In Slave and Genlock mode, this timing is established

by VHSYNC and GHSYNC respectively. The ﬁrst PXCK

following this RESET rising edge is designated as PXCK 1.

Where it is signiﬁcant, reference PXCK timing will be

shown with numbered rising edges. A designation of 2N

clocks refers to an even number of PXCK rising edges from

device reset. If RESET is not shown and clock numbering

does not refer to 2N, timing is relative to signals shown in

the diagram only.

Pixel Data Input Timing

PXCK is internally divided by 2 to generate an internal pixel

clock, PCK which is not accessible from the pins of the

TMC22x91. To ensure the correct phase relationship

between PCK and pixel data, PCK is locked to VHSYNC or

GHSYNC (Slave or Genlock mode, respectively). In Master

mode, VHSYNC is produced on the rising edge of PCK

allowing external circuitry to synchronize the generation of

pixel data and LDV which also operates at the rate of PCK.

The rising edge of LDV clocks the 24-bit pixel data into

three 8-bit registers while PCK clocks that data through the

pixel data path within the TMC22x91. It is therefore neces-

sary to meet the set-up and hold timing between pixel data

and LDV as well as LDV and PCK as shown in Figure 13.

TMC22091 Datasheet(PDF) 36 Page - Cadeka Microcircuits LLC.

TMC22091 Datasheet(HTML) 36 Page - Cadeka Microcircuits LLC.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL