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AM3517 Datasheet(PDF) 39 Page - Texas Instruments |
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AM3517 Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 184 page  AM3517/05 ARM Microprocessor www.ti.com SPRS550 – OCTOBER 2009 Table 2-3. External Memory Interfaces – GPMC Signals Description (ZCN Pkg.) (continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL SUBSYSTEM PIN (ZCN Pkg.) [4] MULTIPLEXING [5] gpmc_d0 GPMC Data bit 0 IO G5 gpmc_a1/ gpmc_d0 gpmc_d1 GPMC Data bit 1 IO G4 gpmc_a2/ gpmc_d1 gpmc_d2 GPMC Data bit 2 IO G3 gpmc_a3/ gpmc_d2 gpmc_d3 GPMC Data bit 3 IO G2 gpmc_a4/ gpmc_d3 gpmc_d4 GPMC Data bit 4 IO G1 gpmc_a5/ gpmc_d4 gpmc_d5 GPMC Data bit 5 IO H2 gpmc_a6/ gpmc_d5 gpmc_d6 GPMC Data bit 6 IO H1 gpmc_a7 /gpmc_d6 gpmc_d7 GPMC Data bit 7 IO J5 gpmc_a8/ gpmc_d7 gpmc_d8 GPMC Data bit 8 IO J4 gpmc_a9/ gpmc_d8 gpmc_d9 GPMC Data bit 9 IO J3 gpmc_a10/ gpmc_d9 gpmc_d10 GPMC Data bit 10 IO J2 gpmc_a11/ gpmc_d10 gpmc_d11 GPMC Data bit 11 IO J1 gpmc_a12/ gpmc_d11 gpmc_d12 GPMC Data bit 12 IO K4 gpmc_a13/ gpmc_d12 gpmc_d13 GPMC Data bit 13 IO K3 gpmc_a14/ gpmc_d13 gpmc_d14 GPMC Data bit 14 IO K2 gpmc_a15/ gpmc_d14 gpmc_d15 GPMC Data bit 15 IO K1 gpmc_a16/ gpmc_d15 gpmc_ncs0 GPMC Chip Select 0 O L2 NA gpmc_ncs1 GPMC Chip Select 1 O L1 NA gpmc_ncs2 GPMC Chip Select 2 O M4 NA gpmc_ncs3 GPMC Chip Select 3 O M3 NA gpmc_ncs4 GPMC Chip Select 4 O M2 NA gpmc_ncs5 GPMC Chip Select 5 O M1 NA gpmc_ncs6 GPMC Chip Select 6 O N5 NA gpmc_ncs7 GPMC Chip Select 7 O N4 NA gpmc_clk GPMC clock O N1 NA gpmc_nadv_ale Address Valid or Address Latch Enable O R1 NA gpmc_noe Output Enable O R2 NA gpmc_nwe Write Enable O R3 NA gpmc_nbe0_cle Lower Byte Enable. Also used for Command O R4 NA Latch Enable gpmc_nbe1 Upper Byte Enable O T1 NA gpmc_nwp Flash Write Protect O T2 NA gpmc_wait0 External indication of wait I T3 NA gpmc_wait1 External indication of wait I T4 NA gpmc_wait2 External indication of wait I T5 NA gpmc_wait3 External indication of wait I U1 NA Table 2-4. External Memory Interfaces – SDRC Signals Description (ZCN Pkg.) SIGNAL NAME[1] DESCRIPTION[2] TYPE[3] BALL (ZCN Pkg.) [4] sdrc_d0 SDRAM data bit 0 IO B21 sdrc_d1 SDRAM data bit 1 IO A21 sdrc_d2 SDRAM data bit 2 IO D20 sdrc_d3 SDRAM data bit 3 IO C20 sdrc_d4 SDRAM data bit 4 IO E19 sdrc_d5 SDRAM data bit 5 IO D19 Submit Documentation Feedback TERMINAL DESCRIPTION 39 |
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