AM3517 datasheet(97/184 Pages) TI

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GPMC_FCLK

gpmc_clk

gpmc_ncsx

gpmc_a[10:1]

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_noe

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

Add0

Add1

Add2

Add3

Add4

OUT

FA1

FA0

FA18

FA13

FA12

FA0

FA9

FA10

FA21

FA20

030-028

FA15

FA14

AM3517/05 ARM Microprocessor

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SPRS550 – OCTOBER 2009

Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1)(2)(3)(4)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside AccessTime register bit field.

(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC

functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge

after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input

page data). FA20 value must be stored in PageBurstAccessTime register bit field.

(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

AM3517 Datasheet(PDF) 97 Page - Texas Instruments

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