AM3517 datasheet(95/184 Pages) TI

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GPMC_FCLK

gpmc_clk

gpmc_ncsx

gpmc_a[10:1]

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_noe

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

Valid Address

Valid

DataIN0

OUT

FA0

FA9

FA10

FA3

FA1

FA4

FA12

FA13

FA0

FA10

FA5

030-026

FA15

FA14

AM3517/05 ARM Microprocessor

www.ti.com

SPRS550 – OCTOBER 2009

(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK

(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

(14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK

Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses

performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR

behavior is automatically handled by GPMC controller.

Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

AM3517 Datasheet(PDF) 95 Page - Texas Instruments

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