AM3517 datasheet(2/184 Pages) TI

2 / 184 page

AM3517/05 ARM Microprocessor

SPRS550 – OCTOBER 2009

www.ti.com

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Interfaces to Double Data Rate (DDR2)

• ARM CortexTM-A8 Memory Architecture

SRAM

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ARMv7 Architecture

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SDRAM Memory Scheduler (SMS) and

• Trust Zone

Rotation Engine

• Thumb-2

• General Purpose Memory Controller (GPMC)

• MMU Enhancements

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16-bit Wide Multiplexed Address/Data Bus

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In-Order, Dual-Issue, Superscalar

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Up to 8 Chip Select Pins With 128M-Byte

Microprocessor Core

Address Space per Chip Select Pin

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NEON Multimedia Architecture

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Glueless Interface to NOR Flash, NAND

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Over 2x Performance of ARMv6 SIMD

Flash (With ECC Hamming Code

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Supports Both Integer and Floating Point

Calculation), SRAM and Pseudo-SRAM

SIMD

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Flexible Asynchronous Protocol Control for

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JAZELLE RCT Execution Environment

Interface to Custom Logic (FPGA, CPLD,

Architecture

ASICs, etc.)

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Dynamic Branch Prediction with Branch

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Nonmultiplexed Address/Data Mode

Target Address Cache, Global history

(Limited 2K-Byte Address Space)

buffer and 8 entry return stack

• Test Interfaces

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Embedded Trace Macrocell [ETM] support

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IEEE-1149.1 (JTAG) Boundary-Scan

for Non_invasive Debug

Compatible

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16K-Byte instruction Cache (4-Way set-

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Embedded Trace Macro Interface (ETM)

associative)

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Serial Data Transport Interface (SDTI)

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16K-Byte Data Cache (4-Way

Set-Associative)

• 65-nm CMOS technology

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256K-Byte L2 Cache

• Applications:

• POWERVR SGX™ Graphics Accelerator

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Single Board Computers

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Tile Based Architecture Delivering up to 10

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Industrial and Home Automation

MPoly/sec

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Digital Signage

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Universal Scalable Shader Engine:

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Point-of-Sale Devices

Multi-threaded Engine Incorporating Pixel

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Portable Media Player

and Vertex Shader Functionality

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Portable Industrial

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Industry Standard API Support: OpenGLES

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Transportation

1.1 and 2.0, OpenVG1.0

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Navigation

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Fine Grained Task Switching, Load

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Smart White Goods

Balancing, and Power Management

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Digital TV

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Programmable, High-Quality Image

Anti-Aliasing

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Digital Video Camera

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Gaming

• Endianess

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Notes:

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ARM Instructions - Little Endian

*Operating condition restrictions apply.

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ARM Data – Configurable

**Different memory controller to support

• SDRC Memory Controller

DDR2. New IP support for VPFE, EMAC,

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16, 32-bit Memory Controller With 1G-Byte

and HECC.

Total Address Space

AM3517/05 ARM Microprocessor

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