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AM3517 Datasheet(PDF) 63 Page - Texas Instruments

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Part # AM3517
Description  ARM Microprocessor
PDF  184 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM3517 Datasheet(HTML) 63 Page - Texas Instruments

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3.3 DC Electrical Characteristics
AM3517/05 ARM Microprocessor
www.ti.com
SPRS550 – OCTOBER 2009
Table 3-4 summarizes the dc electrical characteristics.
Table 3-4. DC Electrical Characteristics(1)
PARAMETER
MIN
NOM
MAX
UNIT
LVCMOS Pin Buffers
VIH
High-level input voltage
vddshv = 1.8 V
0.6 x vddshv
vddshv + 0.3
V
vddshv = 3.3 V
0.6 x vddshv
vddshv + 0.3
VIL
Low-level input voltage
vddshv = 1.8 V
TBD
0.3 x vddshv
V
vddshv = 3.3 V
TBD
0.6
VOH
High-level output voltage(2)
vddshv = 1.8 V
vddshv x 0.2
V
vddshv = 3.3 V
0.75 x vddshv
VOL
Low-level output voltage(2)
vddshv = 1.8 V
0.2
V
vddshv = 3.3 V
0.125 x
vddshv
tT
Input transition time (rise time, tR or fall time, tF evaluated
10
ns
between 10% and 90% at PAD)
II
Input current with VI = VI max
TBD
TBD
A
IOZ
Off-state output current for output in high impedance with driver
TBD
TBD
A
only, driver disabled
Off-state output current for output in high impedance with
TBD
driver/receiver/pullup only, driver disabled, pullup not inhibited
Off-state output current for output in high impedance with
TBD
driver/receiver/pulldown only, driver disabled, pulldown not
inhibited
IZ
Total leakage current through the PAD connection of a
TBD
TBD
A
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
LVCMOS Open-Drain Pin Buffers Dedicated to I2C IOs
VIH
High level input voltage
TBD
TBD
V
VIL
Low level input voltage
TBD
0.6
V
VOL
Low-level output voltage open-drain at 3-mA sink current
TBD
TBD
V
II
Input current at each I/O pin with an input voltage between 0.1 x
TBD
TBD
A
vddshv to 0.9 x vddshv
CI
Capacitance for each I/O pin
TBD
pF
TOF
Output fall time from VIHmin to VILmax with a
Fast mode
TBD
TBD
ns
bus capacitance CB from 10 pF to 400 pF
Standard mode
TBD
Output fall time with a capacitive load from 10 High-speed mode
TBD
TBD
pF to 100 pF at 3-mA sink current
Output fall time with a capacitive load of 400
TBD
TBD
pF at 3-mA sink current
Output fall time with a capacitive load of 40
TBD
pF (for CBUS compatibility)
Complex IO Dedicated to USB
VIH
High-level input voltage
TBD
TBD
V
VIL
Low-level input voltage
TBD
0.6
V
VOH
High-level output voltage at 4-mA sink current
TBD
V
VOL
Low-level output voltage at 4-mA sink current
TBD
V
II
Input current at each I/O pin with an input voltage between 0.1 x
TBD
TBD
A
vddshv to 0.9 x vddshv
CI
Capacitance for each I/O pin
TBD
pF
(1)
Values are subject to change after characterization.
(2)
With 100 A sink / source current at vddsxmin.
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ELECTRICAL CHARACTERISTICS
63



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