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AS8228 Datasheet(PDF) 65 Page - ams AG |
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AS8228 Datasheet(HTML) 65 Page - ams AG |
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65 / 123 page  Data Sheet AS8218 / AS8228 Revision 3.0, 31-May-06 Page 65 of 123 Each protocol starts by putting S_N to low level and ends by putting S_N to high again. If S_N goes high before the normal end of the protocol, the current protocol is terminated, the internal SPI state control logic is reset. The SO line state is X (don’t care). When operating (S_N = 0), the data is shifted out on the falling edge of SC and incoming data is sampled on the rising edge of SC. S_N (out) SC (out) SO (out) T S_N_setup 18 7 6 5 4 3 21 5 4 3 28 7 6 1/f SC=TSC T byte_to_byte T S_N_hold DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 X X Shift out data at SO with falling edge of SC SI (in) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 X X Sample input data SI on rising edge of SC Transfer of 1st Data byte Transfer of 2nd Data byte Figure 10: SPI timing diagram Note: SO is shifted out on the falling edge of SC and SI is sampled on the rising edge (clock scheme: CPHA=1, CIDLE=1). For mcu_clk = 4 MHz (max) Parameter Description MCU_clk cycles Min Units TS_N_setup Time between S_N going low and first SC falling edge 36 9 µs TS_N_hold Time between last SC rising edge and S_N going high 6 1.5 µs Tbyte_to_byte Time between two data bytes (LSB last to MSB next) 12 3 µs TSC SC serial clock period (= 1/FSC) 4 1 µs TSC_LOW SC serial clock minimum low time 2 0.5 µs TSC_HIGH SC serial clock minimum high time 2 0.5 µs SPI Registers Register Name Address Description SSPCON 9400h Control register SSPCLKDIV 9401h Clock divider register SSPSTAT 9402h Status register SSPBUF 9403h Data register |
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