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AS8228 Datasheet(PDF) 69 Page - ams AG |
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AS8228 Datasheet(HTML) 69 Page - ams AG |
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69 / 123 page  Data Sheet AS8218 / AS8228 Revision 3.0, 31-May-06 Page 69 of 123 The SPI interrupt status is captured in the SSPSTAT register. Each interrupt status bit can be masked by the SSPCON register, which is OR-ed to a single SPI interrupt request signal (SPI_IRQ). IE.ESPI (=IE.3) OR ITRA IOVR ICOL IETR, IEOV, IECO SPI_IRQ SSPSTAT SSPCON IE MCU Register Figure 11: Block diagram Data Register (SSPBUF, 9403h) The data-register is an 8-bits wide shift-register with parallel load input and parallel output. It is written and read by the MCU in normal operation and by the bootloader during startup phase. 7 6 5 4 3 2 1 0 Bit parallel SPI_DATAIN from MCU/Bootloader parallel out SPI_DATAOUT to MCU/Bootloader serial in SI serial out SO |
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