AS8228 datasheet(82/123 Pages) AMSCO

82 / 123 page

Data Sheet AS8218 / AS8228

Revision 3.0, 31-May-06

Page 82 of 123

Mode

Examples

Notes

MOV @R0, A

MOVX @DPTR, A

Moves contents of A to location addressed

by R0, or by DPTR

Immediate addressing

MOV R0, #data

Moves immediate #data to R0

Index addressing

MOVC A, @A+DPTR

MOVC A, @A+PC

Moves contents of location addressed by

A+DPTR, or A+PC to A. For reading lookup

tables, applies to program memory only

Interrupt Controller

The 8051 core provides 7 interrupt sources: 2 of them are the same as in the standard 8051, the others are

tied to specific internal sources. Each interrupt causes the program to jump to the corresponding interrupt

vector if the interrupt is enabled in the interrupt enable register (IE). The interrupt priority can be controlled via

the interrupt priority register (IP) in order to override the predefined priority, starting with IP.0 as highest. For

further information on the interrupt sources refer to the appropriate chapters.

Interrupt Enable Register (IE)

Each of the interrupt sources can be individually enabled or disabled by setting the corresponding bit in the IE

once.

MSB

LSB

ERTC

ES2

ESPI

EIOX

ET0

EDSP

Enable bit = 0 disables the interrupt

Enable bit = 1 enables the interrupt

Interrupt Priority Register (IP)

MSB

LSB

PRTC

PS2

PSPI

PIOX

PT0

PDSP

Priority bit = 1 assigns high priority

Priority bit = 0 assigns low priority

Interrupt

Source

RTC

UART2

UART1

SPI

MPIO

Timer 0

DSP

Interrupt

Vector

0033h

002Bh

0023h

001Bh

0013h

000Bh

0003h

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