AS8228 datasheet(46/123 Pages) AMSCO

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Data Sheet AS8218 / AS8228

Revision 3.0, 31-May-06

Page 46 of 123

The Programmable Divider follows a fixed 'Divide by 5' divider, thus the default value to the Programmable

Divider is:

3.579545 / 5 = 715909 (default value to Programmable Divider)

Therefore: A change of 1Hz in this default value is equal to:

1 / 715909 = 1.397 ppm

Measure the deviation in the clk_1Hz frequency output provided by the AS8218 / AS8228 ICs

Assuming an error of +690 ppm is measured (faster than real-time)

Thus +690 / 1.397 = 493.915 = 494

Therefore 494 must be added to the default value:

715909 + 494 = 716403 (dec) = 0A EE 73 (hex)

Divider Register Byte 2 = 0A

Divider Register Byte 1 = EE

Divider Register Byte 0 = 73

The RTC is then calibrated to within +/- 1.4 ppm

Frequency Trimming (9133h)

A further option for clk_1Hz frequency trimming is available. In this case only the 5 lower bits of register

‘Frequency Trim’ (9133h) are used as defined in the following table.

FREQ_TRIM[4:0] Correction [ppm]

Seconds per Day 1

Seconds per Day 2

87.0

81.2

75.4

69.6

63.8

58.0

52.2

46.4

40.6

34.8

29.0

23.2

17.4

11.6

5.8

-5.8

-1

-11.6

-1

-17.4

-1

-2

-23.2

-2

-29.0

-2

-3

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