AMPL138ZCE3 datasheet(36/268 Pages) TI

36 / 268 page

OMAP-L138 Low-Power Applications Processor

SPRS586A – JUNE 2009 – REVISED AUGUST 2009

www.ti.com

Table 3-9. DDR2 Controller (DDR2) Terminal Functions (continued)

SIGNAL

TYPE(1)

PULL(2)

DESCRIPTION

NAME

NO.

DDR_DQS[0]

T14

I/O

IPD

DDR2 data strobe inputs/outputs

DDR_DQS[1]

V11

I/O

IPD

DDR_BA[2]

IPD

DDR_BA[1]

IPD

DDR2 SDRAM bank address

DDR_BA[0]

IPD

DDR2 loopback signal for external DQS gating.

DDR_DQGATE0

R11

IPD

Route to DDR and back to DDR_DQGATE1 with

same constraints as used for DDR clock and data.

DDR2 loopback signal for external DQS gating.

DDR_DQGATE1

R12

IPD

Route to DDR and back to DDR_DQGATE0 with

same constraints as used for DDR clock and data.

DDR2 reference output for drive strength calibration

DDR_ZP

U12

—

of N and P channel outputs. Tie to ground via 50

ohm resistor @ 0.5% tolerance.

DDR voltage input for the DDR2/mDDR I/O buffers.

DDR_VREF

—

Note even in the case of mDDR an external resistor

divider connected to this pin is necessary.

N6, N9, N10,

P7, P8, P9,

DDR_DVDD18

PWR

—

DDR PHY 1.8V power supply pins

P10, R7, R8,

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