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AMPL138ZCE3 Datasheet(PDF) 90 Page - Texas Instruments |
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AMPL138ZCE3 Datasheet(HTML) 90 Page - Texas Instruments |
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90 / 268 page  OMAP-L138 Low-Power Applications Processor SPRS586A – JUNE 2009 – REVISED AUGUST 2009 www.ti.com Table 6-7. OMAP-L138 DSP Interrupts (continued) EVT# Interrupt Name Source 46 UART_INT1 UART1 47 ECAP1 ECAP1 48 T64P1_TINT34 Timer64P1 Interrupt 34 49 GPIO_B2INT GPIO Bank 2 Interrupt 50 PRU_EVTOUT7 PRUSS Interrupt 51 ECAP2 ECAP2 52 GPIO_B3INT GPIO Bank 3 Interrupt 53 MMCSD1_INT1 MMCSD1 SDIO Interrupt 54 GPIO_B4INT GPIO Bank 4 Interrupt 55 EMIFA_INT EMIFA 56 EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller 0 Error Interrupt 57 EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller 0 Error Interrupt 58 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Error Interrupt 59 GPIO_B5INT GPIO Bank 5 Interrupt 60 DDR2_MEMERR DDR2 Memory Error Interrupt 61 MCASP0_INT McASP0 Combined RX/TX Interrupts 62 GPIO_B6INT GPIO Bank 6 Interrupt 63 RTC_IRQS RTC Combined 64 T64P0_TINT34 Timer64P0 Interrupt 34 65 GPIO_B0INT GPIO Bank 0 Interrupt 66 PRU_EVTOUT4 PRUSS Interrupt 67 SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register 68 MMCSD1_INT0 MMCSD1 MMC/SD Interrupt 69 UART2_INT UART2 70 PSC0_ALLINT PSC0 71 PSC1_ALLINT PSC1 72 GPIO_B7INT GPIO Bank 7 Interrupt 73 LCDC_INT LDC Controller 74 PROTERR SYSCFG Protection Shared Interrupt 75 GPIO_B8INT GPIO Bank 8 Interrupt 76 - Reserved 77 - Reserved 78 T64P2_CMPINT0 Timer64P2 - Compare Interrupt 0 79 T64P2_CMPINT1 Timer64P2 - Compare Interrupt 1 80 T64P2_CMPINT2 Timer64P2 - Compare Interrupt 2 81 T64P2_CMPINT3 Timer64P2 - Compare Interrupt 3 82 T64P2_CMPINT4 Timer64P2 - Compare Interrupt 4 83 T64P2_CMPINT5 Timer64P2 - Compare Interrupt 5 84 T64P2_CMPINT6 Timer64P2 - Compare Interrupt 6 85 T64P2_CMPINT7 Timer64P2 - Compare Interrupt 7 86 T64P3_TINTALL Timer64P3 Combined TINT12 and TINT 34 Interrupt 87 MCBSP0_RINT McBSP0 Receive Interrupt 88 MCBSP0_XINT McBSP0 Transmit Interrupt 89 MCBSP1_RINT McBSP1 Receive Interrupt 90 MCBSP1_XINT McBSP1 Transmit Interrupt 91 EDMA3_1_CC0_INT1 EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt Peripheral Information and Electrical Specifications 90 Submit Documentation Feedback |
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