AMPL138ZCE3 datasheet(78/268 Pages) TI

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OSCOUT

OSCIN

OSCVSS

Clock

Input

toPLL

6.6 Clock PLLs

6.6.1

PLL Device-Specific Information

OMAP-L138 Low-Power Applications Processor

SPRS586A – JUNE 2009 – REVISED AUGUST 2009

www.ti.com

Figure 6-7. External 1.2V Clock Source

Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock

PARAMETER

MIN

MAX

UNIT

fCLKIN

OSCIN frequency range

MHz

tc(CLKIN)

Cycle time, external clock driven on OSCIN

tw(CLKINH) Pulse width high, external clock on OSCIN

0.4 tc(CLKIN)

tw(CLKINL)

Pulse width low, external clock on OSCIN

0.4 tc(CLKIN)

tt(CLKIN)

Transition time, OSCIN

The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides

clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the

mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows

the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.

The PLL controller provides the following:

• Glitch-Free Transitions (on changing clock settings)

• Domain Clocks Alignment

• Clock Gating

• PLL power down

The various clock outputs given by the controller are as follows:

• Domain Clocks: SYSCLK [1:n]

• Auxiliary Clock from reference clock source: AUXCLK

Various dividers that can be used are as follows:

• Post-PLL Divider: POSTDIV

• SYSCLK Divider: D1, , Dn

Various other controls supported are as follows:

• PLL Multiplier Control: PLLM

• Software programmable PLL Bypass: PLLEN

The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

Peripheral Information and Electrical Specifications

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