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AMPL138ZCE3 Datasheet(PDF) 15 Page - Texas Instruments |
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AMPL138ZCE3 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 268 page  3.5 DSP Subsystem InstructionFetch C674x Fixed/FloatingPointCPU Register File A Register FileB CacheControl MemoryProtect BandwidthMgmt L1P 256 CacheControl MemoryProtect BandwidthMgmt L1D 64 64 8x32 32KBytes L1DRAM/ Cache 32KBytes L1P RAM/ Cache 256 CacheControl MemoryProtect BandwidthMgmt L2 256KBytes L2RAM 256 1MByte L2ROM 256 CFG MDMA SDMA EMC PowerDown Interrupt Controller IDMA 256 256 256 256 256 64 High Performance SwitchFabric 64 64 64 Configuration Peripherals Bus 32 OMAP-L138 Low-Power Applications Processor www.ti.com SPRS586A – JUNE 2009 – REVISED AUGUST 2009 The DSP Subsystem includes the following features: • C674x DSP CPU • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 256KB Unified Mapped RAM/Cache (L2) • 1MB Mask-programmable ROM • Little endian Figure 3-1. C674x Megamodule Block Diagram Submit Documentation Feedback Device Overview 15 |
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