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6.14.2 McASP Electrical Data/Timing

6.14.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing

OMAP-L138 Low-Power Applications Processor

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SPRS586A – JUNE 2009 – REVISED AUGUST 2009

Table 6-45 and Table 6-47 assume testing over recommended operating conditions (see Figure 6-31 and

Figure 6-32).

Table 6-45. Timing Requirements for McASP0 (1.2V, 1.1V)(1)(2)

1.2V

1.1V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

tc(AHCLKRX)

Cycle time, AHCLKR/X

tw(AHCLKRX)

Pulse duration, AHCLKR/X high or low

tc(ACLKRX)

Cycle time, ACLKR/X

AHCLKR/X ext

20(3)

22(3)

tw(ACLKRX)

Pulse duration, ACLKR/W high or low

AHCLKR/X ext

AHCLKR/X int

11.5

Setup time,

tsu(AFSRX-ACLKRX)

AHCLKR/X ext input

AFSR/X input to ACLKR/X (4)

AHCLKR/X ext output

AHCLKR/X int

-1

-2

Hold time,

th(ACLKRX-AFSRX)

AHCLKR/X ext input

0.4

AFSR/X input after ACLKR/X(4)

AHCLKR/X ext output

0.4

AHCLKR/X int

11.5

Setup time,

tsu(AXR-ACLKRX)

AXR0[n] input to ACLKR/X(4)(5)

AHCLKR/X ext

AHCLKR/X int

-1

-2

Hold time,

th(ACLKRX-AXR)

AHCLKR/X ext input

0.4

AXR0[n] input after ACLKR/X(4)(5)

AHCLKR/X ext output

0.4

(1)

ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1

ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

(2)

P = SYSCLK2 period

(3)

This timing is limited by the timing shown or 2P, whichever is greater.

(4)

McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0

(5)

McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0

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