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EP80579 Datasheet(PDF) 13 Page - Intel Corporation |
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EP80579 Datasheet(HTML) 13 Page - Intel Corporation |
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13 / 1916 page  August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 13 Contents 16.2.1.39 Offset 88h: DRAM_SCICMD - DRAM SCI Command Register ................. 486 16.2.1.40 Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register ................ 487 16.2.1.41 Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register ............ 488 16.2.1.42 Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register........ 490 16.2.1.43 Offset 98h: THRESH_SEC0 - Rank 0 SEC Error Threshold Register .......................................................................... 491 16.2.1.44 Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error Threshold Register .......................................................................... 491 16.2.1.45 Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address Register ........................................................................................ 492 16.2.1.46 Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error Address Register............................................................................. 492 16.2.1.47 Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register............................................................................. 493 16.2.1.48 Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register............................................................................. 493 16.2.1.49 Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error Counter Register............................................................................. 494 16.2.1.50 Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error Counter Register............................................................................. 494 16.2.1.51 Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error Counter Register............................................................................. 495 16.2.1.52 Offset C2h: THRESH_DED - DED Error Threshold Register .................... 495 16.2.1.53 Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct Syndrome Register ......................................................................... 496 16.2.1.54 Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct Syndrome Register ......................................................................... 496 16.2.1.55 Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address Register ........................................................................................ 497 16.2.1.56 Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register....... 497 16.2.1.57 Offset ECh: DERRINJCTL - DRAM Error Injection Control Register .......... 499 16.3 EDMA Registers: Bus 0, Device 1, Function 0 ..................................................... 501 16.3.1 Register Details ..................................................................................... 502 16.3.1.1 Offset 00h: VID - Vendor Identification Register.................................. 502 16.3.1.2 Offset 02h: DID - Device Identification Register .................................. 502 16.3.1.3 Offset 04h: PCICMD - PCI Command Register ..................................... 503 16.3.1.4 Offset 06h: PCISTS - PCI Status Register ........................................... 504 16.3.1.5 Offset 08h: RID - Revision Identification Register ................................ 504 16.3.1.6 Offset 0Ah: SUBC - Sub-Class Code Register ...................................... 505 16.3.1.7 Offset 0Bh: BCC - Base Class Code Register ....................................... 505 16.3.1.8 Offset 0Eh: HDR - Header Type Register ............................................ 505 16.3.1.9 Offset 10h: EDMALBAR - EDMA Low Base Address Register .................. 506 16.3.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register ............... 506 16.3.1.11 Offset 2Eh: SID - Subsystem Identification Register ............................ 506 16.3.1.12 Offset 34h: CAPPTR - Capabilities Pointer Register .............................. 507 16.3.1.13 Offset 3Ch: INTRLINE - Interrupt Line Register ................................... 507 16.3.1.14 Offset 3Dh: INTRPIN - Interrupt Pin Register ...................................... 508 16.3.1.15 Offset 40h: EDMACTL - EDMA Control Register ................................... 508 16.3.1.16 Offset 80h: EDMA_FERR - EDMA First Error Register............................ 508 16.3.1.17 Offset 84h: EDMA_NERR - EDMA Next Error Register ........................... 510 16.3.1.18 Offset 88h: EDMA_EMASK - EDMA Error Mask Register ........................ 512 16.3.1.19 Offset A0h: EDMA_SCICMD - EDMA SCI Command Register ................. 514 16.3.1.20 Offset A4h: EDMA_SMICMD - EDMA SMI Command Register................. 515 16.3.1.21 Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register ............ 516 16.3.1.22 Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register........ 517 16.3.1.23 Offset B0h: MSICR - MSI Control Register .......................................... 518 16.3.1.24 Offset B4h: MSIAR - MSI Address Register ......................................... 519 16.3.1.25 Offset B8h: MSIDR - MSI Data Register ............................................. 520 16.4 PCI Express* Port A Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0 ............................................................................. 521 |
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