EP80579 datasheet(47/1916 Pages) INTEL

47 / 1916 page

August 2009

Intel® EP80579 Integrated Processor Product Line Datasheet

Order Number: 320066-003US

Contents

42.0 Local Expansion Bus Controller.............................................................................1671

42.1 Overview ......................................................................................................1671

42.2 Feature List ...................................................................................................1671

42.3 Block Diagram ...............................................................................................1672

42.4 Theory of Operation........................................................................................1672

42.4.1

Outbound Transfers...............................................................................1672

42.4.1.1

Chip Select Address Allocation .........................................................1673

42.4.1.2

Address and Data Byte Steering ......................................................1675

42.4.1.3

Expansion Bus Interface Configuration..............................................1676

42.4.1.4

Using I/O Wait ..............................................................................1680

42.4.1.5

Parity ...........................................................................................1681

42.4.1.6

Special Design Knowledge for Using HPI mode...................................1681

42.4.1.7

Expansion Bus Outbound Timing Diagrams........................................1682

42.5 Register Summary..........................................................................................1696

42.5.1

Timing and Control Registers ..................................................................1698

42.5.1.1

EXP_TIMING_CS0 - Expansion Bus Timing Register ............................1698

42.5.1.2

EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers .....................1700

42.5.2

Configuration and Status Registers ..........................................................1702

42.5.2.1

EXP_CNFG0 - Configuration Register 0..............................................1702

42.5.2.2

EXP_PARITY_STATUS - Expansion Bus Parity Status Register...............1703

42.6 Performance Estimation ..................................................................................1703

Test and Debug, Volume 5 of 6.................................................. 1707

43.0 Global Design for Test Features ............................................................................1709

43.1 JTAG ...........................................................................................................1709

43.1.1

JTAG Functions Overview ......................................................................1709

43.1.2

EP80579 TAP Controllers ........................................................................1709

43.1.2.1

IA-32 Core....................................................................................1709

43.1.2.2

MCH TAP Extension ........................................................................1709

43.1.3

EP80579 JTAG ID Codes.........................................................................1710

43.1.4

Special Requirements and Limitations ......................................................1710

43.1.5

JTAG Instructions Summary: MCH ...........................................................1710

43.2 I/O Testing ...................................................................................................1713

43.2.1

JTAG Boundary Scan .............................................................................1713

43.2.1.1

Pins Excluded from Boundary Scan Chain ..........................................1713

44.0 IA-32 Core............................................................................................................1715

44.1 JTAG ............................................................................................................1715

44.1.1

Usage..................................................................................................1715

44.1.1.1

Description ...................................................................................1716

45.0 IMCH Design for Test............................................................................................1717

45.1 IMCH Design for Test Features .......................................................................1717

45.1.1

Features .............................................................................................1717

45.2 JTAG ............................................................................................................1717

45.2.1

IMCH JTAG Instructions .........................................................................1717

45.2.1.1

JTAG Chain Details.........................................................................1717

45.3 High Speed I/O Testing ...................................................................................1719

46.0 ICH Design for Test ..............................................................................................1721

46.1 JTAG ............................................................................................................1721

46.2 I/O Test Mode................................................................................................1721

46.2.1

Test Mode Entry Methods .......................................................................1721

46.2.1.1

Non-Functional Test Mode Entry.......................................................1721

46.2.2

Test Mode Registers ..............................................................................1723

46.2.2.1

TEST0 - Test Control Register 0 .......................................................1723

EP80579 Datasheet(PDF) 47 Page - Intel Corporation

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