EP80579 datasheet(53/1916 Pages) INTEL

53 / 1916 page

August 2009

Intel® EP80579 Integrated Processor Product Line Datasheet

Order Number: 320066-003US

Contents

37-16

Transmit Descriptor (TDESC) Layout..................................................................1366

37-17

Legacy Transmit Descriptor (TDESC) Layout .......................................................1366

37-18

Transmit Command (TDESC.CMD) Layout...........................................................1367

37-19

Transmit Status Layout (TDESC.STATUS) ...........................................................1368

37-20

Transmit Special Field Layout (TDESC.SPECIAL) ..................................................1369

37-21

TCP/IP Context Transmit Descriptor (TDESC) - (Type = 0000)...............................1370

37-22

TCP/IP Context Transmit Descriptor Command Field (TDESC.TUCMD).....................1371

37-23

TCP/IP Context Transmit Descriptor Status (TDESC.TUSTATUS).............................1372

37-24

TCP/IP Data Transmit Descriptor Layout (TDESC) - (Type = 0001).........................1373

37-25

TCP/IP Data Transmit Descriptor Command Field (TDESC.DCMD) ..........................1373

37-26

TCP/IP Data Transmit Descriptor Status (TDESC.DSTATUS) ..................................1375

37-27

TCP/IP Data Transmit Descriptor Packet Options Field (TDESC.POPTS) ...................1375

37-28

TCP/IP Data Transmit Descriptor Special Field (TDESC.VLAN)................................1375

37-29

Transmit Descriptor Ring Structure ....................................................................1376

37-30

Transmit Descriptor and TUCMD Field (TDESC) Layouts - (Type = 0000) ................1380

37-31

TCP/IP Packet Format ......................................................................................1382

37-32

TCP/IP Context Transmit Descriptor & Command Layout.......................................1383

37-33

TCP Partial Pseudo-Header Checksum for IPv4 ....................................................1384

37-34

TCP Partial Pseudo-Header Checksum for IPv6 ....................................................1384

37-35

IPv4 Header (Traditional Representation) ...........................................................1385

37-36

IPv4 Header (Little-Endian Order)......................................................................1385

37-37

IPv6 Header (Traditional Representation) ...........................................................1385

37-38

TCP Header (Traditional Representation) ............................................................1386

37-39

TCP Header (Little-Endian Order) ......................................................................1386

37-40

TCP Pseudo Header Content (Traditional Representation)......................................1387

37-41

TCP Pseudo-Header Content for IPv6 .................................................................1387

37-42

UDP Header (Traditional Representation)............................................................1387

37-43

UDP Header (Little-Endian Order) ......................................................................1387

37-44

UDP Pseudo Header Diagram for IPv4 ................................................................1388

37-45

UDP Pseudo-Header Diagram for IPv6 ................................................................1388

37-46

Data Flow.......................................................................................................1391

37-47

802.3x MAC Control Frame Format ....................................................................1398

37-48

TCI Bit Ordering..............................................................................................1401

37-49

Memory Protection in the GbE ...........................................................................1419

37-50

Power State Transitions ...................................................................................1550

37-51

Reset Deasserted after 1st EEPROM Read Completes............................................1552

37-52

Reset Deasserted after before EEPROM Read Completes .......................................1553

37-53

Transition from D0a to D3 and Back without Reset...............................................1554

37-54

Transition from D0a to D3 and Back with Reset ...................................................1555

37-55

Reset without Transition to D3 ..........................................................................1556

39-1

CAN Block Diagram .........................................................................................1570

39-2

Standard CAN Data Frame................................................................................1572

39-3

Extended CAN Data Frame ...............................................................................1574

39-4

Standard CAN Remote Frame............................................................................1575

39-5

Extended CAN Remote Frame ...........................................................................1576

39-6

CAN Timing Parameters ...................................................................................1578

39-7

Bit Rate and Time Settings ...............................................................................1579

39-8

Receive Message Handler .................................................................................1581

39-9

Message Arbitration.........................................................................................1584

41-1

Programming Model.........................................................................................1621

41-2

Example Network Topology...............................................................................1623

41-3

Clock Synchronization......................................................................................1625

41-4

Transparent Clock Switch Protocol Flow..............................................................1627

41-5

Time Stamp Reference Point .............................................................................1632

42-1

Expansion Bus Controller..................................................................................1672

EP80579 Datasheet(PDF) 53 Page - Intel Corporation

EP80579 Datasheet(HTML) 53 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL