EP80579 datasheet(46/1916 Pages) INTEL

46 / 1916 page

Contents

Intel® EP80579 Integrated Processor Product Line Datasheet

August 2009

Order Number: 320066-003US

41.5.4

IEEE1588 over CAN .............................................................................. 1634

41.5.5

Auxiliary Snapshots .............................................................................. 1635

41.5.6

Target Time Expiration .......................................................................... 1636

41.5.7

System Time........................................................................................ 1636

41.5.8

Interrupts............................................................................................ 1637

41.5.9

Reset ................................................................................................. 1637

41.6 Register Summary ......................................................................................... 1637

41.6.1

Detailed Register Descriptions ................................................................ 1639

41.6.1.1

Offset 0000h: TS_Control - Time Sync Control Register ...................... 1639

41.6.1.2

Offset 0004h: TS_Event - Time Sync Event Register .......................... 1641

41.6.1.3

Offset 0008h: TS_Addend - Addend Register..................................... 1643

41.6.1.4

Offset 000Ch: TS_Accum - Accumulator Register............................... 1643

41.6.1.5

Offset 0010h: TS_Test - Time Sync Test Register .............................. 1644

41.6.1.6

Offset 0014h: TS_PPS - PPS Compare Register.................................. 1646

41.6.1.7

Offset 0018h: TS_TSysTimeLo - Raw System Time Low Register ......... 1647

41.6.1.8

Offset 001Ch: TS_RSysTimeHI - Raw System Time High Register ........ 1648

41.6.1.9

Offset 0020h: TS_SysTimeLo - System Time Low Register .................. 1649

41.6.1.10 Offset 0024h: TS_SysTimeHi - System Time High Register.................. 1650

41.6.1.11 Offset 0028h: TS_TrgtLo - Target Time Low Register ......................... 1650

41.6.1.12 Offset 002Ch: TS_TrgtHi - Target Time High Register......................... 1651

41.6.1.13 Offset 0030h: TS_ASMLo - Auxiliary Slave Mode Snapshot

Low Register................................................................................. 1652

41.6.1.14 Offset 0034h: TS_ASMHi - Auxiliary Slave Mode Snapshot

High Register............................................................................... 1653

41.6.1.15 Offset 0038h: TS_AMMSLo - Auxiliary Master Mode Snapshot

Low Register................................................................................. 1654

41.6.1.16 Offset 003Ch: TS_AMMSHi - Auxiliary Master Mode Snapshot High Register .

1655

41.6.1.17 Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control

41.6.1.18 Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event

41.6.1.19 Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register (Per

Ethernet Channel) ......................................................................... 1659

41.6.1.20 Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register (Per

Ethernet Channel) ......................................................................... 1660

41.6.1.21 Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per

Ethernet Channel) ......................................................................... 1661

41.6.1.22 Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register (Per

Ethernet Channel) ......................................................................... 1662

41.6.1.23 Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per

Ethernet Channel) ......................................................................... 1663

41.6.1.24 Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register

(Per Ethernet Channel) .................................................................. 1664

41.6.1.25 Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event

41.6.1.26 Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register (Per

CAN Channel) ............................................................................... 1666

41.6.1.27 Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per

CAN Channel) ............................................................................... 1667

41.6.1.28 Offset 01F0h: TS_Aux_TrgtLo - Auxiliary Target Time Low

41.6.1.29 Offset 01F4h: TS_Aux_TrgtHi -Auxiliary Target Time High

41.6.1.30 Offset 0200h: L2_EtherType - L2 EtherType Register ......................... 1669

41.6.1.31 Offset 0204h: UD_EtherType - User Defined EtherType Register .......... 1669

41.6.1.32 Offset 0208h: UD_Header_Offset - User Defined Header Offset

41.6.1.33 Offset 020Ch: UD_Header - User Defined Header Register .................. 1670

EP80579 Datasheet(PDF) 46 Page - Intel Corporation

EP80579 Datasheet(HTML) 46 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL