EP80579 datasheet(5/1916 Pages) INTEL

5 / 1916 page

August 2009

Intel® EP80579 Integrated Processor Product Line Datasheet

Order Number: 320066-003US

Contents

5.2.1

Hardware Capabilities ............................................................................. 139

5.2.2

Software Usage Model ............................................................................ 141

5.3

Error Reporting by the IMCH ............................................................................. 141

5.3.1

Overview of the First and Next Error Architecture ....................................... 141

5.3.2

Global Error Events ................................................................................ 142

5.3.3

Unit-Level Errors from the Buffer Unit ....................................................... 143

5.3.4

Unit-Level Errors from the DRAM Interface ................................................ 143

5.3.5

Unit-Level Errors from the FSB Interface ................................................... 144

5.3.6

Unit-Level Errors from the NSI ................................................................. 145

5.3.7

Unit-Level Errors from the EDMA Engine.................................................... 146

5.3.8

Unit-Level Errors from PCI Express* Ports A0 and A1 .................................. 147

5.4

Error Reporting by the IICH .............................................................................. 149

5.4.1

SMBus Interface .................................................................................... 149

5.4.2

LPC Interface......................................................................................... 150

5.4.3

USB 1.1 Interface .................................................................................. 151

5.4.4

USB 2.0 Interface .................................................................................. 151

5.4.5

SATA Interface ...................................................................................... 152

5.4.6

Serial I/O Interface ................................................................................ 153

5.5

Error Reporting by the System Memory Controller ............................................... 153

5.5.1

Handling Out-of-Bounds Addresses........................................................... 154

5.5.2

IMCH - Memory Controller ....................................................................... 154

5.6

Error Reporting by AIOC Devices ....................................................................... 155

5.6.1

Gigabit Ethernet MAC ............................................................................. 155

5.6.2

CAN Interface ........................................................................................ 156

5.6.3

SSP Interface ........................................................................................ 157

5.6.4

Local Expansion Bus ............................................................................... 158

5.6.5

IEEE 1588, and GCU............................................................................... 159

6.0

Reset and Power Management............................................................................... 161

6.1

Reset and Powergood Distribution ..................................................................... 161

6.1.1

Types of Reset....................................................................................... 161

6.1.1.1

Powergood Implementation.............................................................. 161

6.1.1.2

Hard Reset Implementation.............................................................. 162

6.1.1.3

Software Controlled Reset................................................................ 162

6.1.1.4

CPU Only Reset Implementation ....................................................... 162

6.1.1.5

S-state Wake Events ....................................................................... 163

6.1.1.6

Targeted Reset Implementation ........................................................ 163

6.1.2

Platform Reset and Powergood................................................................. 163

6.1.2.1

Platform Powergood ........................................................................ 163

6.1.2.2

Platform Reset................................................................................ 163

6.1.2.3

Reset and Powergood Distribution ..................................................... 164

6.1.3

EP80579 Power Sequencing and Reset Sequence........................................ 167

6.2

BIOS Boot Flow (Initialization) .......................................................................... 175

6.2.1

Memory Configuration............................................................................. 176

6.2.2

Memory Initialization .............................................................................. 176

6.2.3

Boot from Network ................................................................................. 176

6.3

Power Management ......................................................................................... 177

6.3.1

Power Management States ...................................................................... 177

6.3.2

Power Management Support .................................................................... 179

6.3.2.1

Transitioning Between Power States .................................................. 181

6.3.2.2

Power State Transition Timing Diagrams ............................................ 181

6.3.3

Thermal Sensor ..................................................................................... 182

6.3.4

ACPI Implementation.............................................................................. 182

7.0

7.1

Overview of Register Descriptions and Summaries ............................................... 183

EP80579 Datasheet(PDF) 5 Page - Intel Corporation

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