EP80579 datasheet(6/1916 Pages) INTEL

6 / 1916 page

Contents

Intel® EP80579 Integrated Processor Product Line Datasheet

August 2009

Order Number: 320066-003US

7.1.1

7.1.2

7.1.3

7.1.4

“Sticky” Register Fields............................................................................ 190

7.2

IA-32 core Registers ........................................................................................ 190

7.3

IMCH and IICH Registers ..................................................................................191

7.3.1

IMCH Registers: Bus 0, Device 0, Function 0 ............................................. 191

7.3.2

IMCH Error Reporting Registers: Bus 0, Device 0, Function 1 ........................ 195

7.3.3

EDMA Engine Registers: Bus 0, Device 1, Function 0 ................................... 197

7.3.4

PCI Express* Port A Registers: Bus 0, Device 2, Function 0 .........................200

7.3.5

PCI Express* Port A1 Registers: Bus 0, Device 3, Function 0 ........................ 203

7.3.6

USB (1.1) Controller: Bus 0, Device 29, Functions 0 ................................... 206

7.3.7

USB (2.0) Controller: Bus 0, Device 29, Function 7 .................................... 207

7.3.8

Root Complex: Bus 0, Device 31, Function 0 ............................................. 209

7.3.9

LPC Interface: Bus 0, Device 31, Function 0 .............................................. 210

7.3.10

SATA Controller: Bus 0, Device 31, Function 2............................................213

7.3.11

SMBus Controller: Bus 0, Device 31, Function 3.......................................... 216

7.3.12

IA-32 Core Interface I/O-Mapped Register ................................................. 217

7.3.13

IMCH PCI Configuration ........................................................................... 217

7.3.14

APIC .....................................................................................................217

7.3.15

8259 Interrupt Controller (PIC) ................................................................ 219

7.3.16

APM Power Management.......................................................................... 219

7.3.17

LPC DMA ............................................................................................... 220

7.3.18

8254 Timers ..........................................................................................221

7.3.19

High Precision Event Timers ..................................................................... 222

7.3.20

Watchdog Timer and Serial I/O................................................................. 222

7.3.21

Real Time Clock......................................................................................223

7.4

AIOC Registers ................................................................................................ 224

7.4.1

PCI-to-PCI Bridge: Bus 0, Device 4, Function 0........................................... 224

7.4.2

Gigabit Ethernet MAC: Bus M, Devices 0, 1, and 2, Function 0 ..................... 226

7.4.3

GCU: Bus M, Device 3, Function 0............................................................. 240

7.4.4

CAN Interface: Bus M, Device 4 and 5, Function 0 ...................................... 242

7.4.5

SSP Interface: Bus M, Device 6, Function 0 ............................................... 245

7.4.6

IEEE 1588 Timestamp Unit: Bus M, Device 7, Function 0 .............................247

7.4.7

Local Expansion Bus Interface: Bus M, Device 8, Function 0: ....................... 249

IA-32 Core and Integrated Memory Controller Hub,

Volume 2 of 6.............................................................................. 251

8.0

IA-32 Core .............................................................................................................253

8.1

Overview ........................................................................................................ 253

8.2

Theory of Operation ......................................................................................... 253

8.2.1

L2 Cache Size ........................................................................................ 253

8.2.2

Platform and JTAG Identifiers ...................................................................253

8.2.3

FSB Physical Interface............................................................................. 254

8.2.4

IA-32 Core and FSB Frequency................................................................. 254

9.0

CMI Introduction ................................................................................................... 255

9.1

System Architecture......................................................................................... 256

9.2

PCI Express*................................................................................................... 256

9.2.1

Supported PCI Express Configurations ....................................................... 257

9.2.1.1

Low power SKU with PCI Express ports removed .................................257

9.3

Supported Debug and Management Interfaces..................................................... 257

9.4

Supported IMCH Integrated Features.................................................................. 257

9.4.1

EDMA Controller ..................................................................................... 257

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