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EP80579 Datasheet(PDF) 48 Page - Intel Corporation

Part # EP80579
Description  Intel짰 EP80579 Integrated Processor Product Line
PDF  1916 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

EP80579 Datasheet(HTML) 48 Page - Intel Corporation

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Contents
Intel® EP80579 Integrated Processor Product Line Datasheet
August 2009
48
Order Number: 320066-003US
46.2.3
XOR Chains ........................................................................................ 1725
Technical Specifications, Volume 6 of 6..................................... 1727
47.0 SKUs, Power Savings and Pre-Boot Firmware ...................................................... 1729
47.1 Overview ...................................................................................................... 1729
47.2 SKUs, Strap Options and Pre-Boot Firmware Programmable Configuration Modes ... 1729
47.2.1
SKU Features ....................................................................................... 1729
47.2.2
DDR2 Frequencies Supported by the EP80579 .......................................... 1731
47.2.3
Strap Options (Platform-based Configuration)........................................... 1731
47.2.4
Pre-Boot Firmware Programmable SKU Options ........................................ 1732
48.0 Package Specifications......................................................................................... 1733
48.1 Package Introduction ..................................................................................... 1733
48.2 Functional Signal Definitions............................................................................ 1733
48.3 JTAG Boundary Scan Chain (BSC) and XOR Chain .............................................. 1733
48.4 Signal Pin Descriptions ................................................................................... 1734
48.4.1
IA-32 Core .......................................................................................... 1736
48.4.1.1
Thermal Diode .............................................................................. 1736
48.4.1.2
Global Clock CRU .......................................................................... 1736
48.4.1.3
Sideband Miscellaneous Signals....................................................... 1737
48.4.2
Integrated Memory Controller Hub (IMCH) ............................................... 1739
48.4.2.1
IMCH Reset .................................................................................. 1739
48.4.2.2
DDR2 SDRAM ............................................................................... 1739
48.4.2.3
PCI Express* ................................................................................ 1741
48.4.3
Integrated I/O Controller Hub (IICH)....................................................... 1744
48.4.3.1
Real Time Clock ............................................................................ 1744
48.4.3.2
General Purpose I/O (GPIO) and Interrupts ...................................... 1744
48.4.3.3
Serial Peripheral Interface (SPI) ...................................................... 1749
48.4.3.4
Low Pin Count (LPC) Interface......................................................... 1749
48.4.3.5
SMBus ......................................................................................... 1750
48.4.3.6
UART Interface ............................................................................. 1751
48.4.3.7
Serial ATA (SATA) Interface............................................................ 1753
48.4.3.8
Universal Serial Bus (USB) Interface ................................................ 1755
48.4.3.9
Power Management Interface.......................................................... 1756
48.4.3.10 IICH Miscellaneous Signals ............................................................. 1758
48.4.4
Acceleration and I/O Complex (AIOC)...................................................... 1759
48.4.4.1
Controller Area Network (CAN) Bus.................................................. 1759
48.4.4.2
Gigabit Ethernet (GbE) Interface ..................................................... 1760
48.4.4.3
Time Division Multiplexing (TDM) Interface ....................................... 1764
48.4.4.4
Local Expansion Bus (LEB) Interface ................................................ 1765
48.4.4.5
Synchronous Serial Port (SSP) Interface........................................... 1768
48.4.4.6
IEEE 1588-2008 Hardware Assist Interface ....................................... 1768
48.4.5
Miscellaneous....................................................................................... 1769
48.4.5.1
JTAG ........................................................................................... 1769
48.4.5.2
Miscellaneous Signals .................................................................... 1770
48.4.5.3
Reserved ..................................................................................... 1770
48.4.5.4
No Connect .................................................................................. 1771
48.4.6
Power ................................................................................................. 1772
48.5 Flip-Chip Ball Grid Array (FCBGA) Package Dimensions ....................................... 1773
48.6 Ball Map Information ...................................................................................... 1778
49.0 Electrical Specifications ....................................................................................... 1819
49.1 Absolute Maximum Ratings ............................................................................. 1820
49.1.1
Input and I/O Pin Undershoot and Overshoot Specifications........................ 1820
49.2 Power Characteristics ..................................................................................... 1823
49.2.1
Power Supply Requirements................................................................... 1823



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