EP80579 datasheet(45/1916 Pages) INTEL

45 / 1916 page

August 2009

Intel® EP80579 Integrated Processor Product Line Datasheet

Order Number: 320066-003US

Contents

40.4.1.3

Frame Format (FRF).......................................................................1609

40.4.1.4

External Clock Select (ECS).............................................................1609

40.4.1.5

Synchronous Serial Port Enable (SSE) ..............................................1609

40.4.1.6

Serial Clock Rate (SCR) ..................................................................1609

40.4.2

SSP Control Register 1...........................................................................1610

40.4.2.1

Offset 04h: SSCR1 - SSP Control Register 1 Details............................1610

40.4.2.2

Receive FIFO Interrupt Enable (RIE).................................................1611

40.4.2.3

Transmit FIFO Interrupt Enable (TIE) ...............................................1611

40.4.2.4

Loop Back Mode (LBM) ...................................................................1611

40.4.2.5

Serial Clock Polarity (SPO) ..............................................................1612

40.4.2.6

Serial Clock Phase (SPH) ................................................................1612

40.4.2.7

National Microwire* Data Size (MWDS) .............................................1613

40.4.2.8

Transmit FIFO Interrupt Threshold (TFT)...........................................1613

40.4.2.9

Receive FIFO Interrupt Threshold (RFT) ............................................1613

40.4.2.10 Enable FIFO Write/Read Function (EFWR)..........................................1613

40.4.2.11 Select FIFO for Enable FIFO Write/Read (STRF)..................................1614

40.4.3

SSP Status Register...............................................................................1614

40.4.3.1

Offset 08h: SSSR - SSP Status Register Details .................................1614

40.4.3.2

Transmit FIFO Not Full Flag (TNF) (Read-Only,

Non-Interruptible)..........................................................................1615

40.4.3.3

Receive FIFO Not Empty Flag (RNE)

(Read-Only, Non-Interruptible) ........................................................1615

40.4.3.4

SSP Busy Flag (BSY) (Read-Only, Non-Interruptible) ..........................1615

40.4.3.5

Transmit FIFO Service Request Flag (TFS) (Read-Only,

Maskable Interrupt) .......................................................................1616

40.4.3.6

Receive FIFO Service Request Flag (RFS) (Read-Only,

Maskable Interrupt) .......................................................................1616

40.4.3.7

Receiver Overrun Status (ROR) (Read/Write,

Non-Maskable Interrupt).................................................................1616

40.4.3.8

Transmit FIFO Level .......................................................................1616

40.4.3.9

Receive FIFO Level.........................................................................1616

40.4.4

SSP Interrupt Test Register ....................................................................1616

40.4.4.1

Offset 0Ch: SSITR - SSP Interrupt Test Register Details ......................1616

40.4.5

SSP Data Register .................................................................................1617

40.4.5.1

Offset 10h: SSDR - SSP Data Register Details....................................1617

41.0 IEEE 1588 Time Synchronization Hardware Assist ................................................1619

41.1 Overview ......................................................................................................1619

41.2 Feature List ...................................................................................................1619

41.2.1

Signal Descriptions................................................................................1620

41.3 Functional Block Diagram ................................................................................1620

41.4 Usage Model ..................................................................................................1622

41.4.1

Channel Mapping ..................................................................................1622

41.5 Functional Description.....................................................................................1622

41.5.1

IEEE 1588 Overview ..............................................................................1622

41.5.1.1

Initialization ..................................................................................1623

41.5.1.2

Time Synchronization .....................................................................1623

41.5.1.3

PTP Message Formats.....................................................................1628

41.5.2

Time Stamping Operation.......................................................................1629

41.5.2.1

Sync Messages ..............................................................................1630

41.5.2.2

Follow-up Messages .......................................................................1630

41.5.2.3

Delay_Req Message .......................................................................1630

41.5.2.4

Delay_Response Messages ..............................................................1631

41.5.2.5

Error Handling...............................................................................1631

41.5.3

IEEE1588 over Ethernet .........................................................................1631

41.5.3.1

Timestamping Mechanism ...............................................................1631

41.5.3.2

PTP Message Detection in Ethernet Frames........................................1632

41.5.3.3

Modes of Operation ........................................................................1633

EP80579 Datasheet(PDF) 45 Page - Intel Corporation

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