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SC68C652B Datasheet(PDF) 12 Page - NXP Semiconductors

Part # SC68C652B
Description  5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface
PDF  43 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC68C652B Datasheet(HTML) 12 Page - NXP Semiconductors

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SC68C652B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 2 November 2009
12 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
6.8 Programmable baud rate generator
The SC68C652B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC68C652B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent transmit/receive channel control. The programmable baud rate generator is
capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is
necessary to use full rail swing on the clock input. The SC68C652B can be configured for
internal or external clock operation. For internal clock oscillator operation, an industry
standard microprocessor crystal is connected externally between the XTAL1 and XTAL2
pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see Table 6).
The generator divides the input 16
× clock by any divisor from 1 to (216 − 1). The
SC68C652B divides the basic external clock by 16. The basic 16
× clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in Table 6 shows the
selectable baud rate table available when using a 1.8432 MHz external clock input.
Fig 3.
Crystal oscillator connection
002aab325
C2
33 pF
XTAL1
XTAL2
X1
1.8432 MHz
C1
22 pF



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