SC68C652B datasheet(16/43 Pages) NXP

16 / 43 page

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

16 of 43

NXP Semiconductors

SC68C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

TSR and UART via the THR, providing that the THR is empty. The THR empty ﬂag in the

LSR register will be set to a logic 1 when the transmitter is empty or when data is

transferred to the TSR. Note that a write operation can be performed when the THR

empty ﬂag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a

Receive Serial Shift Register (RSR). Receive data is removed from the SC68C652B and

receive FIFO by reading the RHR register. The receive section provides a mechanism to

prevent false starts. On the falling edge of a start or false start bit, an internal receiver

counter starts counting clocks at the 16

× clock rate. After 71⁄

2 clocks, the start bit time

should be shifted to the center of the start bit. At this time the start bit is sampled, and if it

is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver

from assembling a false character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the IRQ output pin.

Table 10.

Interrupt Enable Register bits description

Bit

Symbol

Description

IER[7]

CTS interrupt

logic 0 = disable the CTS interrupt (normal default condition)

logic 1 = enable the CTS interrupt. The SC68C652B issues an interrupt

when the CTSn pin transitions from a logic 0 to a logic 1.

IER[6]

RTS interrupt

logic 0 = disable the RTS interrupt (normal default condition)

logic 1 = enable the RTS interrupt. The SC68C652B issues an interrupt

when the RTSn pin transitions from a logic 0 to a logic 1.

IER[5]

Xoff interrupt

logic 0 = disable the software ﬂow control, receive Xoff interrupt (normal

default condition)

logic 1 = enable the software ﬂow control, receive Xoff interrupt

IER[4]

Sleep mode

logic 0 = disable Sleep mode (normal default condition)

logic 1 = enable Sleep mode

IER[3]

Modem Status Interrupt. This interrupt will be issued whenever there is a

modem status change as reﬂected in MSR[3:0].

logic 0 = disable the modem status register interrupt (normal default

condition)

logic 1 = enable the modem status register interrupt

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