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ADS8201IBRGET Datasheet(PDF) 13 Page - Texas Instruments |
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ADS8201IBRGET Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 33 page ![]() ADS8201 www.ti.com SLAS534B – JULY 2009 – REVISED MAY 2010 AUTO TRIGGER (See ADC Trigger SCR, Address 08h, Bits[2:0]) Auto-trigger mode can be selected by writing to the ADC Trigger SCR (see the SCR Register Map). In Auto-Trigger (Modes 4, 5, and 6), Auto-Channel (Modes 5 and 6) or Manual-Channel (Mode 4) selection must be enabled after all the channels have been configured according to the specific application. In Auto-Trigger with Auto-Channel Update and Single-Scan mode (Mode 5), the internal device logic triggers conversions and all selected channels are converted sequentially. After the completion of the selected channel conversions, an SPI command must be issued to initiate the next scan event. In this mode, the FIFO buffer can be enabled or disabled. If the FIFO buffer is enabled and the next scan event is initiated, the contents of the FIFO buffer are overwritten. Ensure that all results from the FIFO buffer have been read before issuing the command to start the next scan event. This mode is useful for applications where an external source triggers the scan event; however, the trigger is not periodic. In Auto-Trigger with Auto-Channel Update and Multi-Scan mode (Mode 6), the internal device logic triggers conversions and all selected channels are converted sequentially. In this mode, if the FIFO buffer is disabled, and the ADS8201 continues to trigger conversions for the selected channels in a cyclical mode until an SPI command is sent to stop the conversion. For example, if channel 4 is selected as the starting channel number, the ADS8201 converts channels 4, 5, 6, 7, 4, 5, 6, 7, etc., until this mode is disabled. If the FIFO buffer is enabled and Interrupt SCR, bit D[1] is set, the ADS8201 issues a scan data ready interrupt. It is important to note that in Mode 6, the FIFO buffer contents must be read when the buffer is full (eight conversions = complete); otherwise, subsequent conversions will overwrite the data in the FIFO buffer. This mode is useful when continuous conversion of the input signals across single or multiple channels is required. Figure 26 illustrates the timing for a shared single-scan and multiple-scan mode event. In Auto-trigger with Manual Channel Update mode (Mode 4), the user must select the next channel. In this mode, the delay mux feature is always enabled. Table 4 and Table 5 summarize the selection options for auto channel update and manual channel update, respectively. This mode is useful when the user wants to have flexibility in the channel selection and does not want to use consecutive channels. The delay-mux feature provides full 100kSPS speed in spite of using manual channel update mode. There are two ways to set up the delay mux in this mode. If using the following sequence, then data from first channel are not repeated: 1. The first channel of interest is set. 2. Mode 4 is selected. 3. The second channel of interest is set within 10µs after setting Mode 4. 4. The CONVST pin is asserted. However, if the second channel of interest is not set within 10µs after triggering the delay mux mode, then the first conversion result should be treated as a dummy conversion because the conversion result from the first channel is repeated twice. Table 4. Auto Channel Update(1) SELECTION OPTION BIT SETTINGS ADC SCR, bit D[1] = '1'; FIFO buffer enabled (as shown in Figure 23) Single-Scan Mode (Mode 5)(1) ADC SCR, bit D[1] = '0'; FIFO buffer disabled (as shown in Figure 23) ADC SCR, bit D[1] = '1'; FIFO buffer enabled (as shown in Figure 24) Multi-Scan Mode (Mode 6)(1) ADC SCR, bit D[1] = '0'; FIFO buffer disabled (as shown in Figure 24) (1) See ADC Trigger SCR:D[2:0]. Table 5. Manual Channel Update(1) SELECTION OPTION BIT SETTINGS Delay mux select (Mode 4) ADC SCR, bit D[1] = '1'; FIFO buffer enabled (as shown in Figure 25) (This is the only option with auto channel ADC SCR, bit D[1] = '0' ; FIFO buffer disabled (as shown in Figure 25) select mode and manual trigger) (1) See ADC Trigger SCR, bits D[2:0]. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): ADS8201 |
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