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HCS12 Datasheet(PDF) 276 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 276 Page - Freescale Semiconductor, Inc |
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276 / 452 page ![]() Instruction Glossary S12CPUV2 Reference Manual, Rev. 4.0 276 Freescale Semiconductor Operation: 1 ⇒ I bit Description: Sets the I mask bit. This instruction is assembled as ORCC #$10. The ORCC instruction can be used to set any combination of bits in the CCR in one operation. When the I bit is set, all maskable interrupts are inhibited, and the CPU will recognize only non-maskable interrupt sources or an SWI. SEI Set Interrupt Mask SEI CCR Details: S X HIN Z V C ––– 1 –––– I: 1; set Source Form Address Mode Object Code Access Detail HCS12 M68HC12 SEI translates to... ORCC #$10 IMM 14 10 P P |
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